Self-Isolating Test Circuit for IC Defect Assessment
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Solution Overview
Problem
Current test structures for integrated circuits fail to accurately assess defect levels and identify prone features for short circuits and open circuits due to their inability to mimic real-world interconnect configurations, photolithographic artifacts, and loading effects, which hinder process improvements and design rule optimization.
Innovation Solution
A test circuit design that includes multiple instances of circuit blocks with serially connected continuity paths and parallel isolation buses, allowing for voltage contrast analysis to detect short circuit defects and assess defect levels by forming interconnect links between isolated conductive elements and isolation buses on a higher metal level than other elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If basic line and space network test circuits are used, then the test circuit design is simple, but the test circuits fail to mimic real interconnect configurations and loading effects
Solution Approach 1:
The patent segments the test circuit into multiple independent circuit blocks, each representing a distinct interconnect configuration type. These blocks are then replicated and arranged in specific patterns within the test circuit, allowing each segment to be tested independently while collectively representing the complexity of real interconnect structures.
Solution Approach 2:
The patent varies key parameters such as line width, spacing, and pattern density across different circuit blocks to create test structures that replicate real interconnect characteristics. By changing these geometric parameters, the test circuit can assess defect levels across different feature sizes and configurations without requiring a completely complex design.
2Ease of manufacture
If photolithographic processes are used to define interconnect patterns, then the manufacturing process is standard, but photolithographic artifacts are generated that make it difficult to design test circuits evaluating worst case elements
Solution Approach 1:
The patent acknowledges photolithographic artifacts as inevitable but designs test circuits that specifically target and evaluate these artifact-prone regions. By focusing test structures on minimum sized features and high-density areas where artifacts occur, the patent converts the harmful effect of artifacts into a beneficial diagnostic capability, allowing direct assessment of defect levels in the most problematic areas.
3Device complexity
If interconnect test circuits are designed without existing interconnect levels, then the test circuit design is simpler, but loading effects from IC components cannot be reproduced
Solution Approach 1:
The patent embeds multiple levels of interconnect structures within the test circuit, with lower-level interconnects representing existing IC interconnects and upper-level interconnects forming the test patterns. This nested arrangement allows the test circuit to simultaneously evaluate defect levels in both the embedded interconnect structures and the test patterns themselves, while reproducing loading effects through the multi-level configuration.
4Device complexity
If conventional interconnect test circuits are used, then the test circuit layout is simpler, but physical locations of defects cannot be identified
Solution Approach 1:
The patent assigns unique spatial identifiers and distinct geometric configurations to each circuit block and interconnect feature within the test circuit. By creating local variations in pattern density, line orientation, and spacing that correspond to specific physical locations, the test circuit enables precise defect location through electrical testing while maintaining an organized and manageable overall layout.
Data Source
AI summary
Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits.