Self-latch sense timing in one-time programmable memory
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Solution Overview
Problem
Conventional one-time programmable (OTP) memories face challenges in accurately timing sense amplifier operations due to variations in device behavior over the life of the device, leading to degraded read performance and increased cycle times, especially since replica cells do not match the main memory cells in electrical characteristics and degrade differently.
Innovation Solution
A self-timed read data path architecture that uses a transition in the data path to latch the data state sensed from an accessed memory cell, eliminating the need for tracking circuits and replica cells, thereby minimizing timing margins and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If tracking circuits and replica cells are used to time sense amplifier operations, then timing precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the tracking circuit and replica cell components from the memory architecture. Instead of using separate replica cells to generate timing signals, the invention uses the actual data transition in the bit line to directly trigger the sense amplifier and latch, eliminating the need for complex timing control circuitry while maintaining timing precision.
Solution Approach 2:
The data transition itself serves the dual purpose of both reading the data and triggering the latch operation. The bit line transition automatically clocks the latch without requiring external timing signals from tracking circuits, making the system self-timing and reducing overall circuit complexity.
2Measurement precision
If tracking circuits and replica cells are used to time sense amplifier operations, then timing precision is improved, but power consumption increases
Solution Approach 1:
The patent removes the tracking circuit and replica cell components from the memory architecture. Instead of using separate replica cells to generate timing signals, the invention uses the actual data transition in the bit line to directly trigger the sense amplifier and latch, eliminating the need for complex timing control circuitry while maintaining timing precision.
Solution Approach 2:
The data transition itself serves the dual purpose of both reading the data and triggering the latch operation. The bit line transition automatically clocks the latch without requiring external timing signals from tracking circuits, making the system self-timing and reducing overall circuit complexity.
3Measurement precision
If replica cells are used to match main memory cells, then timing accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent removes the tracking circuit and replica cell components from the memory architecture. Instead of using separate replica cells to generate timing signals, the invention uses the actual data transition in the bit line to directly trigger the sense amplifier and latch, eliminating the need for complex timing control circuitry while maintaining timing precision.
Solution Approach 2:
Instead of creating replica cells that must match main memory cells, the invention uses the actual data transition from the bit line as the timing signal. This eliminates the need for cell matching while maintaining timing accuracy, as the timing is derived from the actual data reading process itself.
4Reliability
If conventional timing circuits are used, then read operation reliability is improved, but memory cycle time increases
Solution Approach 1:
The sense amplifier and latch operation continue seamlessly as the bit line transition occurs. The latch is triggered automatically by the data transition itself, eliminating idle waiting time associated with conventional timing circuits. The read operation flows continuously from sensing to latching without interruption or artificial delays.
Solution Approach 2:
The data transition itself serves the dual purpose of both reading the data and triggering the latch operation. The bit line transition automatically clocks the latch without requiring external timing signals from tracking circuits, making the system self-timing and reducing overall circuit complexity.
Data Source
AI summary
A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.