Self-Management Component Offloads Micro Management in NAND Memory

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Solution Overview

Problem

Current semiconductor memory systems face challenges in improving performance and reliability due to the heavy burden on memory controllers from managing all tasks, including simple operations, which leads to limited bandwidth and potential errors from excessive communication.

Innovation Solution

A self-management design for NAND memory systems, incorporating counters, devoted memories, and a self-management component that performs micro-management tasks, allowing the memory controller to focus on upper-level tasks and reducing communication overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the memory controller manages all tasks including simple operations, then comprehensive control is achieved, but the bandwidth is limited and communication overhead increases

Engineering Contradiction:
ImprovebandwidthVSAvoidcontroller burden
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides management tasks into two levels: macro management handled by the memory controller and micro management handled by the self-management component within the memory device. This segmentation offloads simple operations from the controller, reducing communication overhead and improving bandwidth utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory device incorporates a self-management component that autonomously performs micro-management tasks such as tracking operation information, managing wear leveling, and handling error correction without requiring constant controller intervention. This self-service capability reduces the controller's burden and minimizes communication requirements.

Inventive Principle:
Principle #25Self-service

2Reliability

If the memory controller handles all management tasks, then centralized control is maintained, but errors may occur from excessive communication

Engineering Contradiction:
Improveerror reductionVSAvoidcommunication overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The self-management component within the memory device autonomously handles micro-management operations, reducing the frequency and volume of communications with the controller. This minimizes communication-related errors while maintaining system reliability through localized decision-making.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback mechanisms where the self-management component monitors and reports status information to the controller only when necessary. This selective feedback approach reduces communication overhead while maintaining reliable system operation through continuous local monitoring.

Inventive Principle:
Principle #23Feedback

3Productivity

If simple operations are managed by the controller, then unified management is achieved, but performance is limited due to controller bottleneck

Engineering Contradiction:
ImproveperformanceVSAvoidcontroller workload
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

Management operations are segmented into macro management (controller) and micro management (self-management component). Simple operations are handled locally by the self-management component, freeing the controller to focus on complex tasks and improving overall system performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of autonomy by embedding a self-management component within the memory device. This creates a hierarchical management structure where routine operations are handled at the device level, reducing controller workload and improving performance without sacrificing ease of operation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11036627B2Self-management memory system and operating method thereof
Publication Date: 2021.06.15 SK HYNIX INC
  • US11036627B2 patent drawing
  • US11036627B2 patent drawing
  • US11036627B2 patent drawing

AI summary

A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.