Self-Ordering FFT Algorithm for SIMD Engines
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Solution Overview
Problem
Conventional Fast Fourier Transform (FFT) algorithms require bit-reversal operations, leading to non-contiguous memory access and inefficiencies in SIMD engines, which increases power consumption and computational overhead due to wide data width accesses.
Innovation Solution
The Self-Ordering FFT (SOS-FFT) algorithm performs incremental intra-vector permutations at each stage, eliminating the need for accessing non-contiguous memory elements by using write-back multiplexers to achieve linear ordering of elements without incurring vector memory access overhead, ensuring all memory access is contiguous.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional in-place DIF-FFT implementation is used, then computational efficiency is improved through SIMD operations, but memory access becomes non-contiguous requiring bit-reversal operations
Solution Approach 1:
The patent applies preliminary action by performing bit-reversal permutation in advance during the FFT computation stages. Each stage's output is automatically permuted to produce the correct input ordering for the next stage, eliminating the need for separate bit-reversal operations after the FFT completes. This preliminary reordering of data within vectors ensures contiguous memory access patterns throughout the computation.
Solution Approach 2:
The patent uses write-back multiplexers as intermediary components that facilitate the automatic permutation of data. These multiplexers act as mediators between the computational stages, routing data to the correct memory locations based on pre-computed permutation tables. This intermediary mechanism enables efficient data reordering without requiring complex control logic or additional memory access operations.
2Manufacturing precision
If bit-reversal operations are performed to reorder outputs, then correct output ordering is achieved, but power consumption increases due to wide data width memory accesses
Solution Approach 1:
The patent performs the bit-reversal permutation action preliminarily during the FFT computation stages rather than as a separate post-processing operation. By embedding the permutation within the computational stages themselves and using write-back multiplexers to route data to correct locations, the system achieves correct output ordering without requiring additional wide data width memory accesses that would increase power consumption.
3Speed
If vector memory access is used for FFT operations, then computational speed is improved, but memory bandwidth requirements increase due to non-contiguous access patterns
Solution Approach 1:
The patent applies preliminary permutation of data within vectors during the FFT computation stages. This pre-reordering ensures that subsequent memory accesses follow contiguous patterns, allowing the vector memory to operate at full speed without requiring additional bandwidth for non-contiguous access. The write-back multiplexers handle the data routing, maintaining high computational speed while optimizing memory bandwidth utilization.
Data Source
AI summary
A method for self-ordering Fast Fourier Transform for Single Instruction Multiple Data engines includes performing a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector, the second input vector, the first output vector and the second output vector are each comprised of complex numbers, and a first order of the complex numbers of the first output vector is non-linear and a second order of the complex numbers of the second output vector is non-linear. A combination of complex numbers is reordered and exchanged between the first output vector and the second output vector to partially linearize the first order of the first output vector and to partially linearize the second order of the second output vector.