Self-Powering Latch Structure for Leakage Power Reduction
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Solution Overview
Problem
As integrated chip technology advances, leakage power as a percentage of overall power usage increases, necessitating efficient mechanisms for reducing power consumption, particularly DC leakage power.
Innovation Solution
A method and circuit for implementing power saving self-powering down latch operation, featuring a master slave latch with a virtual power supply connection and a driver gate that combines self-power down and latch data output signals to control connection devices, allowing for power down modes while maintaining latch state during self-power down and flush functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If channel length is reduced to advance integrated chip technology, then processing speed and integration density are improved, but leakage power increases as a percentage of overall power usage
Solution Approach 1:
The latch circuit performs preliminary action by pre-charging the virtual power supply node before the power-down mode is activated. This ensures that the latch state is preserved in the capacitive nodes even as the virtual power supply voltage drops to zero, allowing the circuit to recover its state after power-down without losing the stored data
Solution Approach 2:
The invention dynamically changes the voltage parameter of the virtual power supply connection from a positive voltage level to zero during power-down mode. This parameter change effectively disconnects the power supply from the latch circuit, eliminating leakage power consumption while maintaining the latch state through the previously stored charge in the capacitive nodes
2Loss of energy
If virtual power supply voltage is lowered to reduce leakage power, then power consumption is reduced, but latch state must be maintained during power down mode
Solution Approach 1:
The latch circuit performs preliminary action by pre-charging the virtual power supply node before the power-down mode is activated. This ensures that the latch state is preserved in the capacitive nodes even as the virtual power supply voltage drops to zero, allowing the circuit to recover its state after power-down without losing the stored data
Solution Approach 2:
The virtual power supply connection acts as a temporary, disposable power source that is intentionally allowed to discharge to zero voltage during power-down mode. This temporary power connection enables the latch to maintain its state during the power-down period without requiring continuous power supply, effectively using a short-living power source to achieve long-term power savings
3Loss of energy
If connection control devices are used to implement power down mode, then leakage power is reduced, but device complexity increases
Solution Approach 1:
The connection control devices serve multiple functions: they act as switches to disconnect the power supply during power-down mode, they control the charging and discharging of the virtual power supply node, and they help maintain the latch state. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity
Solution Approach 2:
The latch circuit implements self-service by using its own internal nodes and existing transistors to control the power-down process. The connection control devices are integrated within the latch structure itself, allowing the circuit to manage its own power consumption without requiring external control mechanisms, thus minimizing the increase in overall device complexity
Data Source
AI summary
A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.