Self-Protective Layer on High-k Dielectric for FinFET Patterning
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Solution Overview
Problem
In the semiconductor industry, particularly during the fabrication of FinFET devices, the challenge lies in accurately controlling the deposition and patterning processes for metal gate stacks in advanced process nodes with complex surface topologies and diverse materials, which can lead to inadequate protection of gate dielectric layers, resulting in deteriorated electrical performance.
Innovation Solution
The implementation of a self-protective layer formed using an etching solution containing phosphoric acid and boric acid, which reacts with the gate dielectric layers to create metal phosphate and silicon-boronate complex agents, effectively protecting the layers from further etching and ensuring precise patterning and interface control during the replacement gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for metal gate stack patterning, then patterning can be performed, but the gate dielectric layers are inadequately protected resulting in deteriorated electrical performance
Solution Approach 1:
A self-protective layer is formed on the gate dielectric layers before the patterning process. This layer is created by exposing the gate dielectric layers to an etching solution containing phosphoric acid and boric acid, which reacts with metal elements in the gate dielectric to form metal phosphate and silicon-boronate complex agents. This preliminary protective layer prevents further etching during subsequent patterning steps, thereby protecting the gate dielectric layers while enabling precise patterning.
Solution Approach 2:
The self-protective layer acts as an intermediary between the gate dielectric layers and the etching environment. It is formed by chemical reaction products (metal phosphate and silicon-boronate complex agents) that create a protective barrier, allowing the patterning process to proceed without directly exposing the gate dielectric layers to harmful etchants, thus maintaining both patterning precision and electrical performance.
2Productivity
If the etching process continues without automatic stopping, then complete patterning can be achieved, but the gate dielectric layers are over-etched resulting in loss of material and deteriorated device performance
Solution Approach 1:
The self-protective layer provides automatic stopping of the etching process. Once the protective layer is formed on the gate dielectric layers through the initial exposure to etching solution, it prevents further etching of the underlying gate dielectric material. This self-limiting mechanism ensures that the etching process stops automatically at the desired interface, maintaining precise interface control without requiring additional monitoring or control steps.
3Adaptability or versatility
If different materials are used for gate dielectric layers in different device regions, then device performance can be optimized, but controlling the deposition and patterning processes becomes more difficult
Solution Approach 1:
The self-protective layer formation process is universal and works with different gate dielectric materials (such as high-k materials like hafnium oxide, zirconium oxide, and their silicate variants). The etching solution containing phosphoric acid and boric acid reacts with metal elements in various gate dielectric materials to form protective layers, providing a single versatile process that handles multiple material types without requiring material-specific process adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures the integrity and effectiveness of the gate dielectric layers by automatically stopping the etching process, thereby enhancing the electrical performance and reliability of the metal gate structures in FinFET devices.
Implementation Method 1
reacts with the gate dielectric layers to create metal phosphate and silicon-boronate complex agents
Data Source
AI summary
Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further comprises a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer comprises metal phosphate and the second self-protective layer comprises boron comprising complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.