Self-Reconfiguring Storage Controllers Eliminate I/O Bottlenecks

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Solution Overview

Problem

Legacy Storage Area Network (SAN) and RAID technologies struggle to meet the increasing demands for high data access speeds and capacity, leading to a performance gap between compute and storage systems, which limits system utilization and is costly.

Innovation Solution

The introduction of self-reconfiguring storage controllers and a multi-level storage architecture, along with new hardware and firmware features, allows for improved data access performance without additional HDDs or SSDs, decoupling I/O performance from storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If legacy SAN and RAID technologies are used, then storage capacity can be increased, but data access speed fails to match CPU and memory performance improvements

Engineering Contradiction:
Improvedata access speedVSAvoidsystem utilization
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The storage controller is divided into multiple independent I/O processing channels, each capable of handling I/O operations autonomously. This segmentation allows parallel processing of multiple I/O requests simultaneously, increasing overall data access speed and eliminating the bottleneck of single-threaded controller processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional time-division multiplexing to a spatial parallelism architecture where multiple I/O channels operate concurrently. This dimensional change from sequential to parallel processing enables data access speeds that can keep pace with CPU performance improvements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If more storage controllers are added to increase I/O performance, then data access speed improves, but system complexity and cost increase

Engineering Contradiction:
ImproveI/O performanceVSAvoidcontroller architecture
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Multiple I/O processing channels are merged within a single storage controller, allowing the controller to handle multiple I/O operations simultaneously through internal parallelization. This approach achieves the performance benefits of multiple controllers without the associated increase in system complexity and cost.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each I/O channel within the controller is designed to be universal and multi-functional, capable of handling various I/O operations and protocols. This multi-functionality allows a single controller with multiple channels to replace what would traditionally require multiple specialized controllers, reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If traditional time division multiplexing is used in SAN systems, then device complexity is reduced, but aggregate data rate of attached disk drives is underutilized

Engineering Contradiction:
Improveaggregate data rate utilizationVSAvoidI/O access delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The multiple I/O channels enable continuous and concurrent data transfer operations, eliminating the idle periods inherent in time-division multiplexing. By allowing parallel I/O operations across multiple channels, the system maintains continuous useful action, fully utilizing the aggregate data rate of attached storage devices without the time losses associated with sequential access.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250130714A1Scalable data access system and methods of eliminating controller bottlenecks
Publication Date: 2025.04.24 RADOVANOVIC BRANISLAV
  • US20250130714A1 patent drawing
  • US20250130714A1 patent drawing
  • US20250130714A1 patent drawing

AI summary

A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance. The nFE_SAN and FE_SAN controllers facilitate Converged I/O Interface by simultaneously supporting storage I/O and network traffic.