Self-Rectifying Resistive Memory with Schottky Barrier
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Solution Overview
Problem
Three-dimensional vertical resistive memory devices face challenges in integrating diodes, leading to read crosstalk due to low-impedance current leakage paths, and most self-rectifying devices are not compatible with CMOS processes, requiring high operation voltages above 6V, which is not suitable for logic devices operating at 5V.
Innovation Solution
A self-rectifying resistive memory structure is developed, comprising a lower electrode, a resistive material layer, a barrier layer made of semiconductor or insulating materials, and an upper electrode forming a Schottky contact to achieve self-rectification, with a barrier layer thickness of 2 nm to 5 nm and operation voltage below 5V, allowing for CMOS process compatibility without additional gate transistors or diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is connected in series with R to form a 1T1R structure, then read crosstalk is suppressed, but device complexity increases and additional gate transistors are required
Solution Approach 1:
The patent extracts the rectification function from a separate transistor component and integrates it directly into the resistive memory cell structure. By forming a Schottky contact at the interface between the resistive material and the upper electrode, the rectification capability is built-in, eliminating the need for external transistors while maintaining read crosstalk suppression
Solution Approach 2:
The patent merges the rectification function with the resistive memory cell by creating a Schottky contact at the electrode-resistive material interface. This combines the storage function (R) and rectification function (D) into a single integrated structure (1D1R), reducing device complexity while maintaining reliability
2Ease of manufacture
If self-rectifying devices are fabricated under standard processes, then CMOS compatibility is achieved, but operation voltage exceeds 5V
Solution Approach 1:
The patent modifies the physical parameters of the barrier layer, specifically controlling its thickness to be between 2-5 nm. This parameter change enables the Schottky contact to achieve self-rectification at lower voltage levels (below 5V) while remaining compatible with standard CMOS fabrication processes
Solution Approach 2:
The patent applies a thin barrier layer (2-5 nm) specifically at the interface between the resistive material and upper electrode where the Schottky contact is formed. This localized modification creates the necessary rectification properties without affecting the overall device structure or requiring high operation voltages
3Use of energy by moving object
If a barrier layer with thickness of 2 nm to 5 nm is used, then operation voltage is reduced below 5V, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a barrier layer as an intermediary component between the resistive material and upper electrode. This barrier layer serves as a mediator that enables precise control of the Schottky contact properties through its thickness (2-5 nm), allowing voltage reduction while providing a clear structural feature for manufacturing control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-rectifying resistive memory effectively suppresses read crosstalk, enables high-density integration in both two-dimensional and three-dimensional arrays, reduces costs, and operates within the 5V voltage range, suitable for embedded applications, while maintaining resistive characteristics.
Implementation Method 1
an upper electrode formed on the barrier layer to achieve Schottky contact with the insulating material of the barrier layer; wherein, the Schottky contact between the upper electrode and the insulating material of the barrier layer is used to realize self-rectification
Data Source
AI summary
The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.