Self-Reference Sensing for Variable Resistance Memory Read Latency
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Solution Overview
Problem
Conventional sensing schemes for variable resistance memory cells face challenges in accurately discriminating between high and low resistance states, leading to increased read errors as the size of memory cells decreases, and they suffer from longer read latency due to the need for external reference resistors.
Innovation Solution
The implementation of a self-reference sensing scheme that writes and reads data simultaneously, using a driving control circuit, a resistance monitoring circuit, and a sense amplifying circuit to monitor changes in resistance values within the memory cell, reducing the reliance on external reference resistors and minimizing read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sensing schemes are used with external reference resistors, then measurement precision is maintained, but read latency increases
Solution Approach 1:
The patent extracts and eliminates the external reference resistors from the sensing system by implementing self-reference sensing. The memory cell itself serves as the reference, removing the need for separate external reference components and reducing read latency.
Solution Approach 2:
The memory cell performs dual functions: storing data and serving as its own reference for sensing. This multi-functionality eliminates the need for dedicated external reference resistors, simplifying the device structure and reducing read operations time.
2Productivity
If memory cell size is reduced for miniaturization, then productivity increases, but measurement precision deteriorates
Solution Approach 1:
The memory cell performs self-reference sensing, where the cell itself provides the reference signal for sensing its own resistance state. This self-service approach maintains measurement precision in miniaturized cells by eliminating variability introduced by external reference components.
Solution Approach 2:
The patent utilizes changes in resistance parameters of the memory cell itself as a reference, rather than relying on external physical reference resistors. This parameter-based self-reference maintains discrimination precision even as cell dimensions are reduced for higher density.
3Speed
If self-reference sensing is implemented, then read latency is reduced, but device complexity increases
Solution Approach 1:
The patent merges the reference generation function with the memory cell itself, combining data storage and reference provision into a single cell. This integration reduces the number of separate components and can simplify the overall device architecture despite the sophisticated sensing sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces read errors and shortens read latency by allowing simultaneous writing and reading operations, improving the overall performance of semiconductor memory devices.
Implementation Method 1
a variable resistance element exhibiting different resistance values representing different digital information and outputting, to a corresponding bit line, a cell voltage corresponding to a resistance value of the variable resistance element
Implementation Method 2
a resistance monitoring circuit coupled to the memory cell array and operable to receive the cell voltage of the selected memory cell and output a monitoring voltage based on the cell voltage at the bit line, the monitoring voltage corresponding to a change in the resistance value during the sensing operation
Data Source
AI summary
An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell array of a plurality of memory cells each including a variable resistance element and outputting, to a corresponding bit line, a cell voltage corresponding to a resistance value of the variable resistance element; a driving control circuit operable to control a reference data to be written in a selected memory cell among the memory cells, during a sensing operation; a resistance monitoring circuit operable to receive the cell voltage of the selected memory cell and output a monitoring voltage based on the cell voltage at the bit line, the monitoring voltage corresponding to a change in the resistance value during the sensing operation; and an amplifying circuit operable to amplify the monitoring voltage and output an amplified monitoring voltage as output data.