Self Refresh Control Unit for Semiconductor Memory Devices
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Solution Overview
Problem
Volatile semiconductor memory devices like DRAMs face data loss due to insufficient charge storage during write operations and inefficient refresh cycles, leading to weak cells that can lose data, especially when refresh cycles are slow or power consumption is high.
Innovation Solution
A semiconductor memory device with a self refresh control unit that operates in two modes: a first self refresh mode with shorter cycles and higher voltages to firmly restore data in weak cells, and a second self refresh mode with longer cycles and lower voltages to reduce power consumption and extend data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the refresh cycle is slow, then power consumption is reduced, but data loss occurs in weak cells
Solution Approach 1:
The patent implements dynamic refresh cycle adjustment by switching between first refresh mode (shorter cycle) and second refresh mode (longer cycle) based on operational conditions. The self refresh control unit dynamically selects the appropriate refresh mode to balance power consumption and data retention requirements.
Solution Approach 2:
The patent changes the refresh cycle parameter based on operational mode. In the first refresh mode, a shorter refresh cycle is used to ensure data retention in weak cells, while in the second refresh mode, a longer refresh cycle is used to reduce power consumption when data retention requirements are less critical.
2Reliability
If the refresh cycle is fast, then data retention is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the refresh cycle speed based on the operational state. During active operation, the first refresh mode with faster refresh cycles maintains data retention. During idle or low-power states, the system transitions to the second refresh mode with slower refresh cycles to reduce power consumption.
Solution Approach 2:
The patent implements periodic refresh operations with different periods depending on the operational mode. The self refresh control unit periodically switches between fast refresh (first mode) and slow refresh (second mode) based on timing signals and operational conditions, optimizing the balance between data retention and power consumption.
3Speed
If insufficient charge is stored in memory cell during write, then write speed is improved, but data loss occurs in weak cells
Solution Approach 1:
The patent applies preliminary action by performing additional refresh operations on potentially weak cells before they lose data. The self refresh control unit proactively identifies and refreshes cells that may have insufficient charge, preventing data loss before it occurs.
Solution Approach 2:
The system uses feedback from the refresh operation results to adjust future refresh behavior. Cells that require frequent refreshing are identified as weak cells, and the self refresh control unit increases the refresh frequency for these specific cells to prevent data loss while maintaining overall system performance.
Data Source
AI summary
A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one first core voltage to the memory core unit and to control a self refresh operation to be performed at every first self refresh cycle, in a first self refresh mode, and to apply at least one second core voltage to the memory core unit and to control the self refresh operation to be performed at every second self refresh cycle, in a second self refresh mode. In the semiconductor memory, a level of the at least one first core voltage is higher than that of a corresponding one of the at least one second core voltage, and the first self refresh cycle is shorter than the second self refresh cycle.