Self-Refresh Impedance Driver Circuit Power Management
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Solution Overview
Problem
Current SDRAM circuit power management fails to adequately reduce power consumption while complying with the JEDEC Standard, as some memory controller circuits cannot be powered down during self-refresh mode due to the requirement of a clock enable signal.
Innovation Solution
A self-refresh adjustable impedance driver circuit that selectively adjusts impedance based on memory self-refresh information, providing suitable memory interface signals to comply with SDRAM standards and reduce power consumption by increasing impedance during self-refresh mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory controller circuits are powered down during SDRAM self-refresh mode, then power consumption is reduced, but the JEDEC Standard cannot be complied with because a clock enable signal must be provided
Solution Approach 1:
The patent changes the impedance parameter of the driver circuit during self-refresh mode. By increasing the output impedance of the clock enable signal driver, the circuit can maintain the required logical low voltage level without actively driving the signal, thereby reducing power consumption while still complying with the JEDEC Standard requirement to provide the clock enable signal during self-refresh mode
2Use of energy by moving object
If impedance is increased during self-refresh mode, then power consumption is reduced, but signal integrity may be compromised
Solution Approach 1:
The patent dynamically changes the impedance parameter based on the operational mode. During self-refresh mode, the output impedance is increased to reduce power consumption. During normal operational modes, the output impedance is decreased to ensure proper signal driving capability and maintain signal integrity. This conditional parameter change resolves the contradiction between power savings and signal integrity
Data Source
AI summary
A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information.