Self-Refresh Memory Controller with Time-Gap Command Pairs
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Solution Overview
Problem
High power consumption in semiconductor memory devices, particularly in high-density DRAMs, due to frequent refresh operations required for finite data retention, which increases energy usage in portable electronic devices.
Innovation Solution
Implementing a memory system with a memory controller that transmits self-refresh entry and exit commands to a semiconductor memory device, allowing for a predetermined time gap between these commands, enabling the refresh control circuit to perform refresh operations on all memory cell rows without using auto-refresh commands, thereby reducing current consumption during the refresh period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If auto-refresh commands are used continuously to maintain data retention in high-density DRAM, then data retention is ensured, but power consumption increases significantly
Solution Approach 1:
The patent implements periodic self-refresh operations where the memory device autonomously performs refresh at predetermined intervals without continuous external auto-refresh commands. The memory controller enters a self-refresh mode and the device internally manages refresh operations periodically, reducing the frequency of refresh commands and associated power consumption while maintaining data retention.
Solution Approach 2:
The memory device is empowered to perform self-refresh operations autonomously without requiring continuous external control. Once the memory controller initiates self-refresh mode, the memory device internally generates refresh commands and executes refresh operations on its own, eliminating the need for continuous external auto-refresh command issuance and reducing control overhead.
2Reliability
If refresh operations are performed frequently to ensure data retention, then data reliability is maintained, but normal access operations are disrupted
Solution Approach 1:
Refresh operations are scheduled periodically during self-refresh mode at predetermined intervals rather than continuously. This periodic execution allows normal read/write access operations to proceed uninterrupted between refresh cycles, maintaining both data retention and access efficiency without frequent disruptions.
Solution Approach 2:
The self-refresh mode enables continuous normal access operations to the memory device while refresh operations are performed in the background at periodic intervals. This allows the memory system to maintain productivity and data retention simultaneously without one operation disrupting the other.
Data Source
AI summary
A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.