Self-Repair Logic for Stacked Memory TSV Yield
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Solution Overview
Problem
The manufacturing of 3D stacked memory devices faces significant yield loss and increased costs due to defective through-silicon vias (TSVs), which are critical in interconnecting stacked silicon chips, leading to a higher discard rate of entire memory packages and increased production expenses.
Innovation Solution
Incorporating self-repair logic that utilizes spare TSVs to dynamically replace defective TSVs through error correction codes and data redirection, minimizing hardware overhead and allowing full operation of stacked memory devices with TSV defects, thereby enhancing manufacturing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacked memory devices are manufactured with multiple coupled memory die layers, then memory density is improved, but manufacturing yield deteriorates due to defective through-silicon vias
Solution Approach 1:
The patent incorporates spare TSVs and self-repair logic during the initial manufacturing stage, before defects occur. This preliminary preparation enables the system to detect and repair defective TSVs during operation, thereby maintaining high manufacturing yield while achieving high memory density through multi-layer stacking.
Solution Approach 2:
The patent changes the operational state of TSVs by introducing redundancy. Instead of relying on a fixed one-to-one mapping between TSVs and memory elements, the system dynamically reconfigures connections using spare TSVs, allowing the same physical structure to adapt to different defect scenarios and maintain reliability.
2Reliability
If spare TSVs are incorporated for self-repair, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-repair logic that automatically detects and repairs defective TSVs without external intervention. The system uses built-in test circuits and redundancy management logic to identify defects and activate spare TSVs autonomously, improving reliability while avoiding the need for complex external repair mechanisms.
Solution Approach 2:
The patent divides the TSV infrastructure into functional segments: data TSVs for normal operation and spare Tsvs for repair. This segmentation allows the system to isolate and repair individual defective TSVs without affecting the entire memory structure, managing complexity through modular organization of redundant components.
3Ease of manufacture
If defective TSVs are discarded without repair, then manufacturing cost is reduced, but productivity deteriorates due to higher discard rate
Solution Approach 1:
By implementing self-repair capability, the system eliminates the need for manual inspection and repair of defective TSVs, reducing labor costs and simplifying the manufacturing process. The automatic detection and repair mechanisms enable high-volume production while maintaining high yield, as defective devices can be corrected during or after assembly without requiring complete package discard.
Data Source
AI summary
Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.