Self-Resetting Clock Generator Circuit for Low-Power SRAM
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Solution Overview
Problem
Existing clock generator circuits in self-timed SRAM/RF arrays consume significant power when the memory is idle or not accessed, and are sensitive to process variations and voltage/temperature changes, leading to inefficiencies and potential failures.
Innovation Solution
A self-resetting clock generator circuit with a feedback mechanism that terminates the internally generated clock pulse, using a keeper-free clock gate and NAND gate-based reset circuit to reduce power consumption and improve robustness across various process, voltage, and temperature conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing clock generator topologies are used in self-timed SRAM/RF arrays, then the circuit can generate internal clock signals for memory operations, but the circuit consumes significant power when the memory is idle or not accessed
Solution Approach 1:
The clock generator circuit is designed to produce clock signals only during active memory operations rather than continuously. The circuit responds to write enable (WE) and read enable (RE) signals to generate periodic clock pulses only when needed, eliminating continuous operation and associated power consumption during idle periods
Solution Approach 2:
The circuit uses self-resetting functionality where the clock generator automatically resets its internal state after generating clock pulses for memory operations. The reset mechanism is integrated into the clock generation logic itself, eliminating the need for external reset circuits and ensuring the circuit returns to a low-power state autonomously
2Reliability
If existing clock generator circuits are used, then internal clock signals can be generated for SRAM/RF array operations, but the circuits are sensitive to process variations and voltage/temperature changes
Solution Approach 1:
The clock generator circuit incorporates delay elements and timing control mechanisms that automatically adjust clock pulse width and timing parameters based on process, voltage, and temperature conditions. The circuit monitors operational conditions and modifies clock signal characteristics dynamically to maintain reliable operation across PVT corners without requiring complex external calibration circuits
3Productivity
If conventional clock generator topologies are used, then clock signals can be provided to SRAM/RF arrays, but the circuits have high power consumption during idle periods
Solution Approach 1:
The clock generator operates in a periodic manner, activating only during memory write or read operations triggered by WE and RE signals. During idle periods between operations, the circuit remains in a low-power standby state, dramatically reducing idle power loss while maintaining readiness for rapid operation activation
Solution Approach 2:
The design extracts and removes the continuous operation requirement from the clock generator, allowing it to function only during discrete memory operations. The circuit separates active clock generation from idle standby states, eliminating unnecessary power consumption during non-operational periods
Data Source
AI summary
An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.