Self-Resetting LFSR Clock Divider With Lower Delay and Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LFSR-based clock signal frequency dividers face delays and increased IC footprint due to the presence of OR gates and multiplexers, which limit their operating frequency and power efficiency.
Innovation Solution
The proposed solution eliminates the OR gate from the RESET path and reduces the number of multiplexers by using a single multiplexer and flip-flops with select inputs to manage initial states, allowing for higher frequency operation and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate multiplexers are used to introduce initial valid state into LFSR, then the LFSR can be reset to initial state, but the speed of the clock divider is reduced due to delays
Solution Approach 1:
The patent combines the initial state loading function with the existing flip-flop structure by utilizing the clear inputs of the flip-flops. Instead of using separate multiplexers to introduce the initial state, the design merges the state reset functionality directly into the flip-flop clear mechanism, eliminating the multiplexer delay path and allowing high-speed operation while maintaining the ability to reset to initial state.
Solution Approach 2:
The patent extracts the initial state loading function from the data path by using dedicated clear inputs on the flip-flops. This separates the reset operation from the normal data flow through multiplexers, allowing the initial state to be loaded independently without introducing delay into the critical timing path of the LFSR operation.
2Reliability
If OR gate is used to detect invalid state and end-of-sequence state, then the LFSR can be controlled to generate valid states, but the IC footprint and power consumption increase
Solution Approach 1:
The patent merges the invalid state detection and end-of-sequence detection functions into a single detection mechanism. By using the same tap outputs and logic structure to detect both the all-zero invalid state and the all-one end state, the design eliminates the need for separate OR gate circuits, reducing IC footprint while maintaining reliable control of valid state generation.
Solution Approach 2:
The detection circuit is designed to serve multiple functions: it detects invalid states, detects end-of-sequence states, and controls both types of events using the same hardware structure. This multi-functional approach reduces the overall circuit complexity and power consumption while maintaining reliable control over the LFSR operation.
3Reliability
If additional OR gate and multiplexers are added to handle state detection and resetting, then the LFSR can manage invalid and end states, but power consumption increases
Solution Approach 1:
The patent extracts the state management control signals from the main data path and generates them independently using dedicated detection logic. By taking out the control function from the power-intensive multiplexer and OR gate structure, the design reduces power consumption while maintaining full state management capability through the clear input mechanism of the flip-flops.
Solution Approach 2:
The design uses tapped outputs from the LFSR shift register that are already present in the structure to detect invalid and end states. By copying these existing signal levels through simple logic gates rather than using additional multiplexers and OR gates, the patent reduces power consumption while maintaining reliable state detection and management functionality.
Data Source
AI summary
Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.