Self-Restoring Logic Cells for High-Speed SEU Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Radiation Hard By Design (RHBD) electronic technologies are ineffective at sub 100 nm process nodes due to limitations in speed and Single Event Upset (SEU) tolerance, as they rely on slower recovery processes that impact operating speeds and are not suitable for modern transistor spacing, leading to increased errors and power consumption.
Innovation Solution
The implementation of Self Restoring Logic (SRL) circuits, which utilize CMOS transistors and asynchronous sequential circuits with three internal state variables and additional inverters to ensure that at most one internal state variable is affected by a Single Event Upset (SEU), allowing for immediate correction and continued digital processing without waiting for SEU dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RHBD storage cells are used to tolerate SEU impacts, then fault tolerance is improved, but circuit recovery time increases to 2 ns or more, limiting operating speed to less than 500 MHz
Solution Approach 1:
The invention segments the state variable storage into multiple distributed storage locations within the latch cell. Instead of storing each state variable in a single location, the circuit distributes the storage across multiple transistors and nodes, allowing the system to tolerate SEU impacts in one location while maintaining overall functionality and enabling faster recovery through parallel operation of multiple segments.
Solution Approach 2:
The circuit is designed with preliminary protective structures (distributed storage locations and redundant paths) that are prepared in advance to handle SEU events. When an SEU occurs, the pre-configured distributed architecture immediately provides alternative storage locations and recovery paths, eliminating the need for slow sequential recovery processes and enabling continuous high-speed operation.
2Productivity
If transistor feature sizes are reduced to increase density and speed, then productivity and speed are improved, but tolerance to Single Event Upsets decreases due to radiation and noise sources
Solution Approach 1:
The invention applies segmentation by dividing the state variable storage into multiple distributed locations within each latch cell. This distributed architecture allows modern sub-100nm transistors to be used for high density and speed while maintaining SEU tolerance, as the segmented structure prevents a single SEU event from corrupting the entire state variable and enables rapid recovery through the redundant distributed storage locations.
3Manufacturing precision
If conventional RHBD cell designs are used with modern sub 100 nm processes, then manufacturing precision is improved, but the circuit speed is limited by the slow SEU recovery process
Solution Approach 1:
The circuit incorporates preliminary protective architecture with distributed storage locations and redundant paths that are prepared in advance. This allows the circuit to maintain high-speed operation at modern manufacturing precision levels without being bottlenecked by slow SEU recovery, as the pre-configured distributed structure provides immediate alternative paths when SEU events occur.
Data Source
AI summary
Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circuits are realized with SRL storage cells driving succeeding SRL storage cells directly or through combinational logic such that the corruption of any one internal state variable in the driving SRL cell and it's the associated combinational output logic can affect at most one internal state variable of the succeeding SRL cell. An SRL circuit does not allow propagation of single SEU faults.