Self-Scheduling Multi-Threaded Processor for Memory Latency Tolerance
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Solution Overview
Problem
Existing computing systems face limitations in computation processing speed, energy efficiency, and heat dissipation, particularly when handling sparse data sets and compute-intensive kernels like Fast Fourier Transforms and finite impulse response filters, which require high parallel processing and are sensitive to memory latency.
Innovation Solution
A self-scheduling, multi-threaded processor architecture with a hybrid computing system that allows threads to execute instructions independently of memory latency, featuring a core control circuit that automatically schedules instructions and manages thread execution across local or remote compute elements, enabling efficient execution of compute-intensive tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional computing systems process compute-intensive kernels with sparse data sets, then processing speed is improved, but cache hit rates deteriorate and memory latency increases
Solution Approach 1:
The system segments computation into multiple independent threads that can execute in parallel. Each thread processes a portion of the sparse data set, allowing the processor to maintain high instruction throughput even when individual threads experience cache misses. The segmentation of work into manageable thread units enables efficient utilization of available processing resources while tolerating memory latency.
Solution Approach 2:
The multi-threaded architecture ensures continuity of useful action by allowing other threads to execute while one thread waits for memory access. This keeps the processor pipeline full and maintains high instruction throughput despite memory latency. The system continuously performs useful computation across multiple threads rather than stalling the entire processor.
2Productivity
If existing computing systems increase computation processing capabilities, then performance is improved, but energy consumption and heat dissipation worsen
Solution Approach 1:
The self-scheduling processor automatically manages thread execution and resource allocation without requiring external intervention. The processor monitors its own execution state and dynamically schedules threads to maintain high utilization while minimizing idle cycles. This self-service capability enables the system to achieve high computational throughput with optimized energy efficiency, as the processor adapts its operation to actual workload demands rather than operating at fixed high power states.
3Productivity
If a processor architecture implements significant parallel processing, then productivity is improved, but device complexity worsens
Solution Approach 1:
The processor implements a universal thread execution model that can handle various types of compute-intensive workloads through the same multi-threaded architecture. The self-scheduling mechanism and thread management infrastructure provide multi-functional capability, allowing the same hardware to efficiently process different kinds of kernels (FFT, FIR filters, graph analytics) without requiring specialized processing units for each application type.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.