Self-Scheduling Multi-Threading Processor for Memory Latency
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Solution Overview
Problem
Existing computing systems face limitations in computation processing speed, energy efficiency, and heat dissipation, particularly when handling sparse data sets and compute-intensive kernels like Fast Fourier Transforms and finite impulse response filters, which require high performance and energy efficiency without data reuse, and are intolerant to memory latency.
Innovation Solution
A self-scheduling, multi-threaded processor architecture that allows threads to execute instructions while others wait for memory responses, with dynamic thread management and interconnection networks for efficient energy control, enabling high sustained instruction execution and parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing computing systems are used for compute-intensive kernels, then processing capability is limited, but increasing computation speed increases energy consumption and heat dissipation
Solution Approach 1:
The system segments computation into multiple threads that can be executed in parallel across different processor cores. Each thread handles a portion of the compute-intensive kernel, allowing the system to divide the computational workload and distribute it across multiple execution units, thereby increasing overall processing speed while managing energy consumption through parallel execution
Solution Approach 2:
The processor dynamically adjusts thread scheduling and execution based on runtime conditions. The self-scheduling mechanism monitors system state and dynamically allocates computational tasks to available cores, optimizing the balance between computation speed and energy consumption by activating only the necessary processing units
2Speed
If cache is used for data access, then access speed is improved, but sparse data sets cause poor cache hit rates
Solution Approach 1:
The system transitions from relying on spatial locality (cache-based access) to temporal locality through multi-threading. By executing multiple threads in parallel, the system ensures that while one thread may experience cache misses with sparse data, other threads can utilize the cache effectively, maintaining high data access speed through dimensional diversification of access patterns
3Productivity
If multi-threaded processing is implemented, then parallel processing capability is improved, but system complexity increases
Solution Approach 1:
The processor implements self-scheduling capability where the system automatically manages thread creation, assignment, and execution without external intervention. The core control circuit autonomously monitors processor core availability and dynamically assigns threads to cores, reducing the complexity burden on external software while maintaining high parallel processing capability
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.