Self-Scheduling Processor with Hybrid Threading Fabric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computing systems face limitations in processing speed, energy efficiency, and heat dissipation, particularly when handling sparse data sets and compute-intensive kernels like Fast Fourier Transforms and finite impulse response filters, which require high parallel processing and are sensitive to memory latency.
Innovation Solution
A self-scheduling processor architecture with a hybrid threading fabric that uses work descriptor packets to manage thread execution, allowing for dynamic scheduling and execution of threads across local or remote compute elements, even in the presence of memory latency, and includes a core control circuit to automatically schedule instructions and manage thread states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If threads wait for memory response, then memory access completeness is ensured, but instruction execution throughput decreases
Solution Approach 1:
The system segments the thread execution workflow into multiple independent phases: instruction issuance, memory access initiation, and result validation. The core control circuit can issue subsequent instructions in the pipeline while previous instructions await memory responses, effectively segmenting the waiting period from the active execution periods of other threads.
Solution Approach 2:
The self-scheduling processor maintains continuous useful action by allowing multiple threads to be in different stages of execution simultaneously. When one thread waits for memory, another thread can be executing instructions, ensuring the processor core remains continuously productive rather than idle during memory latency periods.
2Speed
If multiple threads are executed in parallel, then processing speed increases, but energy consumption increases
Solution Approach 1:
The system dynamically adjusts the number of active threads based on memory latency conditions and computational workload. The self-scheduling processor can activate or deactivate threads dynamically, running fewer threads when memory latency is high and energy efficiency is critical, and activating more threads when computational throughput is the priority.
Solution Approach 2:
The core control circuit changes operational parameters such as thread priority, scheduling frequency, and execution batch size based on system state. When energy efficiency is prioritized, the system reduces the parallel thread count or increases the interval between thread activations, effectively using parameter changes to balance speed and energy consumption.
3Productivity
If self-scheduling is implemented, then instruction execution efficiency improves, but system complexity increases
Solution Approach 1:
The core control circuit implements self-service by autonomously scheduling instructions without external intervention. It automatically monitors thread states, manages memory access coordination, and adjusts scheduling decisions based on system feedback, thereby improving execution efficiency while containing complexity within a dedicated control unit rather than distributing it throughout the entire system.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.