Self-Scheduling Processor Hybrid Threading Fabric Memory Latency
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Solution Overview
Problem
Existing computing systems face limitations in computation processing speed, energy consumption, and heat dissipation, particularly when handling sparse data sets and compute-intensive kernels like Fast Fourier Transforms and finite impulse response filters, which require high performance and energy efficiency while tolerating memory latency.
Innovation Solution
A self-scheduling processor with a hybrid threading fabric that allows threads to execute instructions independently of memory responses, enabling high sustained instruction execution per clock and efficient energy use through dynamic reconfiguration and interconnection networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional computing systems are used to process sparse data sets, then computation processing is performed, but cache hit rates are poor and memory latency is not tolerated
Solution Approach 1:
The system segments computation into multiple independent threads that can execute in parallel. Each thread processes a portion of the sparse data set, allowing the system to maintain high instruction throughput even when individual threads experience memory latency. The self-scheduling processor divides work descriptors into multiple threads, enabling continuous execution without stalling the entire system.
Solution Approach 2:
The hybrid threading fabric dynamically switches between different thread execution states, allowing threads to be paused, resumed, or redirected based on memory availability. This dynamic thread management enables the system to tolerate memory latency by switching to other ready threads while waiting for memory responses, maintaining high sustained instructions per clock.
2Productivity
If compute-intensive kernels like FFTs and FIR filters are executed, then high performance is required, but energy consumption increases
Solution Approach 1:
The system applies local quality by executing different types of computations in specialized processing regions. Compute-intensive kernels like FFTs and FIR filters are executed in regions optimized for arithmetic operations, while data movement and memory management are handled in separate regions. This spatial separation allows high performance computation while minimizing energy consumption by keeping data local and reducing memory access frequency.
Solution Approach 2:
The self-scheduling processor uses periodic work descriptor packets to trigger batch processing of compute-intensive kernels. Instead of continuous execution, computation is organized into periodic bursts separated by memory access phases. This periodic execution pattern allows the system to achieve high performance for kernels while reducing average energy consumption by allowing power management during idle periods.
3Productivity
If high parallel processing is implemented, then computation speed increases, but device complexity increases
Solution Approach 1:
The hybrid threading fabric implements a universal thread execution mechanism that handles multiple thread types and workloads through a single unified architecture. Rather than creating separate hardware paths for different computation types, the system uses a universal thread scheduler and execution unit that can dynamically adapt to various kernels and data patterns. This universality achieves high parallel processing capability while controlling device complexity by avoiding redundant specialized hardware.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.