Self-Scheduling Processor Memory Request Management
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Solution Overview
Problem
Existing computing systems face limitations in computation processing speed, energy consumption, and heat dissipation, particularly when handling sparse data sets and compute-intensive kernels like Fast Fourier Transforms and finite impulse response filters, which require high performance and energy efficiency while tolerating memory latency.
Innovation Solution
A self-scheduling processor architecture with a multi-threaded, hybrid computing system that allows for dynamic reconfiguration and efficient energy management, enabling threads to execute instructions despite memory latency and supporting parallel processing across heterogeneous computing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-threading is implemented to improve processing throughput, then productivity increases, but device complexity increases
Solution Approach 1:
The processor is segmented into multiple independent threads that can execute instructions in parallel. Each thread maintains its own program counter and execution state, allowing the processor to divide work into concurrent execution units. This segmentation enables multiple threads to share the processor resources while maintaining independent execution paths, thereby increasing throughput without requiring separate physical processors.
Solution Approach 2:
The processor core is designed to be universal by implementing a single processor unit that can execute multiple threads across different applications and workloads. The core control circuit and execution units are configured to handle diverse instruction types and thread states within a unified architecture, providing multi-functionality that improves productivity while avoiding the complexity of multiple specialized processing units.
2Speed
If cache memory is used to improve data access speed, then speed increases, but use of energy increases
Solution Approach 1:
The system implements partial caching by selectively caching only those data elements that are likely to be reused, rather than caching all data. The cache memory is configured to store data based on access patterns and reuse probability, providing speed improvement for frequently accessed data while avoiding the energy cost of maintaining a full cache for all data elements. This partial action approach balances speed and energy consumption.
3Speed
If parallel processing is implemented to improve computation speed, then speed increases, but loss of time increases due to memory latency
Solution Approach 1:
The processor maintains continuity of useful action by implementing thread switching that allows other threads to execute during memory latency periods. When one thread experiences memory latency, the core control circuit switches to another thread that can execute independently, ensuring that the processor continues performing useful computation rather than stalling. This continuous execution masks the impact of memory latency on overall computation speed.
Solution Approach 2:
The system performs preliminary actions by pre-fetching data into cache memory before it is actually needed by the executing thread. The core control circuit anticipates future data requirements and initiates memory access operations in advance, so that when the data is needed, it is already available in the cache, eliminating latency. This preliminary action reduces the impact of memory access time on computation speed.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.