Self-Scheduling Processor for Multi-Threaded Latency Tolerance
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Solution Overview
Problem
Existing computing systems face limitations in computation processing capabilities, particularly in speed, energy consumption, and heat dissipation, and struggle with sparse data sets that cause poor cache hit rates and latency tolerance, necessitating a high-performance, energy-efficient architecture for compute-intensive applications like FFTs and FIR filters.
Innovation Solution
A self-scheduling processor architecture with a multi-threaded, hybrid computing system that allows threads to execute instructions independently of memory latency, featuring a core control circuit that automatically schedules instructions and manages thread execution across a network, enabling efficient parallel processing and dynamic resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems process sparse data sets, then computation is performed, but cache hit rates deteriorate and memory latency increases
Solution Approach 1:
The system segments computation into multiple independent threads that can execute in parallel. Each thread processes portions of sparse data sets independently, allowing the processor to maintain high instruction throughput even when individual threads experience cache misses. The multi-threaded architecture divides the workload so that while some threads wait for memory, others continue executing, effectively masking memory latency.
Solution Approach 2:
The processor dynamically switches between multiple threads based on their execution state and memory access patterns. When one thread encounters a cache miss and stalls, the processor dynamically activates another thread to execute, creating a dynamic execution flow that maintains high utilization of execution resources despite varying cache performance across different data sets.
2Speed
If existing computing systems increase computation speed, then processing capability improves, but energy consumption and heat dissipation worsen
Solution Approach 1:
The multi-threaded processor ensures continuous useful action by maintaining multiple threads in various execution states. While some threads are executing instructions, others are fetching from memory or waiting for cache responses. This continuity ensures that execution units remain actively productive rather than idle, improving energy efficiency by maximizing the ratio of useful computation to total energy consumption.
Solution Approach 2:
The processor employs partial action by allowing threads to execute independently without requiring synchronized memory access. Threads can proceed with computation using available data while memory operations complete asynchronously, eliminating the need to wait for complete data sets before starting computation. This partial execution model reduces energy consumption by avoiding idle waiting states.
3Reliability
If a processor waits for memory responses, then data accuracy is ensured, but execution throughput deteriorates
Solution Approach 1:
The processor segments memory access operations across multiple threads, so that not all threads are blocked by memory responses simultaneously. Each thread independently manages its own memory access timeline, allowing the system to maintain data accuracy for each thread while achieving high aggregate throughput through parallel execution of multiple threads at different stages of their execution cycles.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.