Self-Scheduling Processor Thread Priority Management
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Solution Overview
Problem
Existing computing systems face limitations in computation processing capabilities, particularly in speed, energy consumption, and heat dissipation, and are inadequate for advanced applications like artificial intelligence and compute-intensive tasks such as Fast Fourier Transforms and finite impulse response filters, which require high performance and energy efficiency with tolerance for memory latency.
Innovation Solution
A self-scheduling processor architecture with a multi-threaded, hybrid computing system that allows threads to execute instructions independently of memory responses, featuring a core control circuit for automatic scheduling and thread management, enabling high sustained instruction execution and efficient energy use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional computing systems are used to process compute-intensive tasks, then they can execute instructions, but they suffer from poor cache hit rates and high memory latency that limit performance
Solution Approach 1:
The system segments computation into multiple independent threads that can execute in parallel. Each thread is assigned to different processing elements, allowing the system to continue executing other threads while waiting for memory responses, thereby hiding memory latency and improving overall instruction throughput
Solution Approach 2:
The system performs preliminary actions by pre-fetching data and pre-positioning threads in ready states before execution. Threads are prepared and queued in advance, allowing the processor to immediately begin execution without waiting for memory operations to complete, thus reducing the impact of memory latency on productivity
2Power
If computing power is increased to handle advanced applications, then processing capability improves, but energy consumption and heat dissipation increase significantly
Solution Approach 1:
The system dynamically adjusts the activation and deactivation of processing elements based on workload requirements. Instead of continuously operating at high power, processing elements are activated only when needed and placed in low-power states when idle, maintaining high computation capability when required while reducing energy consumption during lighter loads
Solution Approach 2:
The system maintains continuous useful computation by keeping multiple threads in various stages of execution simultaneously. While some threads are executing computationally intensive operations, others are being prepared or waiting for memory responses, ensuring that processing elements remain productive without requiring peak power continuously
3Productivity
If more threads are executed in parallel to improve performance, then computation throughput increases, but thread management complexity increases
Solution Approach 1:
The system implements self-service through automatic thread scheduling and management mechanisms. The processor automatically selects which threads to execute next, manages thread states, and handles resource allocation without requiring complex external control, thereby enabling high parallel processing capability while keeping management complexity manageable through automation
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.