Self-Scheduling Reconfigurable Computing Fabric for Energy Efficiency
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Solution Overview
Problem
Existing computing systems face limitations in performance and energy efficiency for compute-intensive tasks such as Fast Fourier Transforms and finite impulse response filters, particularly in applications like synthetic aperture radar, 5G base stations, and machine learning, requiring a more dynamic and configurable architecture.
Innovation Solution
A multi-threaded, coarse-grained configurable computing architecture with self-scheduling and self-reconfiguration capabilities, utilizing a combination of synchronous and asynchronous networks, configuration memories, and control circuits to manage thread execution and data path configurations dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for compute-intensive tasks, then basic computation can be performed, but performance and energy efficiency are insufficient
Solution Approach 1:
The patent implements dynamic reconfiguration of the computing fabric, allowing the system to adapt its architecture runtime based on workload requirements. Configuration memories store multiple data path configurations that can be loaded dynamically, enabling the system to optimize its structure for different compute-intensive tasks such as FFTs and FIR filters, thereby improving both performance and energy efficiency
Solution Approach 2:
The computing fabric is divided into multiple independent compute elements (CEs) that can be individually configured and activated. Each CE can be programmed with different functions through configuration memories, allowing selective activation of only the necessary computing resources for a given task, reducing overall energy consumption while maintaining high productivity
2Adaptability or versatility
If computing systems are made more configurable to handle various applications, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent employs a universal computing fabric where identical compute elements can be configured to perform different functions through programmable logic. The same hardware structure can be reconfigured for FFTs, FIR filters, graph analytics, or other compute-intensive tasks, providing high adaptability without proportionally increasing device complexity
Solution Approach 2:
The system achieves configurability by changing parameters stored in configuration memories rather than physically reconfiguring the hardware architecture. By modifying the data stored in configuration memories, the system can switch between different computational functions and data path configurations, enabling versatile application support with controlled complexity
3Loss of energy
If dynamic reconfiguration is implemented, then energy efficiency improves, but control complexity increases
Solution Approach 1:
The computing fabric incorporates self-scheduling capabilities where compute elements can autonomously determine their execution order and data dependencies. The system includes automatic thread management and runtime reconfiguration features that reduce the burden on external controllers, enabling energy-efficient operation without proportionally increasing control complexity
Solution Approach 2:
The system implements feedback mechanisms through asynchronous signaling and backpressure control, allowing compute elements to communicate their status and requirements dynamically. This enables the control circuitry to make informed decisions about resource allocation and reconfiguration, optimizing energy efficiency while maintaining manageable control complexity through intelligent feedback loops
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.