Self-Scheduling Thread Creation Across Local and Remote Compute Elements

The computing system is segmented into multiple processing elements (PEs) that can operate independently and in parallel. Each PE can handle specific compute-intensive tasks, distributing the computational load across multiple units rather than concentrating it in a single processor, thereby improving overall processing speed while managing energy consumption more efficiently across the distributed architecture.

The patent introduces a third dimension to traditional von Neumann architecture by adding a spatial dimension through the interconnection network that directly connects processing elements to memory and I/O resources. This dimensional expansion allows multiple PEs to access memory and peripherals simultaneously through dedicated pathways, reducing contention and improving both speed and energy efficiency by eliminating the single-bus bottleneck.

Each processing element is equipped with its own local control logic and thread management capabilities, allowing it to independently create, manage, and execute multiple threads without requiring centralized control. This self-service approach enables parallel processing across multiple PEs while keeping individual PE complexity manageable, as each unit handles its own thread lifecycle independently.

The processing elements are designed as universal, multi-functional units that can execute various types of instructions and handle different thread states within a unified architecture. This universality allows the same PE to perform multiple functions (integer processing, floating-point operations, memory access, I/O control) reducing the need for specialized hardware and thereby managing device complexity while maintaining high parallel processing capability.

Each processing element is equipped with its own private cache memory locally coupled to it, rather than sharing a single centralized cache. This local cache configuration allows each PE to cache data specific to its computational tasks, improving cache hit rates for sparse data sets by maintaining locally relevant data without being displaced by other PEs' data access patterns. The local quality of each cache is optimized for its specific PE's workload.

The cache memory system is segmented into multiple private caches distributed across different processing elements rather than a single shared cache. This segmentation allows each PE to have dedicated cache space for its sparse data sets, eliminating cache thrashing and hit rate deterioration caused by multiple PEs competing for the same cache resources. Each segment serves its specific computational needs independently.

The computing architecture is segmented into multiple processing elements distributed across the chip or system, with each PE generating less heat individually than a single high-performance processor would. This spatial distribution of computational workloads allows heat to be dissipated across multiple locations rather than concentrated in one hot spot, managing thermal loads more effectively while maintaining high overall computation speed.

The patent introduces an interconnection network as an intermediary layer between processing elements and memory/I/O resources, enabling efficient data transfer without requiring high-performance processors to be physically close to memory. This intermediary architecture allows computation and memory access to be decoupled spatially, enabling high computation speed in PEs while managing heat dissipation through distributed architecture and reduced thermal coupling between components.