Self-Selecting Memory Array Layout to Block Cell-to-Cell Voltage Transfer
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Solution Overview
Problem
Existing memory devices face reliability issues due to voltage transfer between adjacent selected and unselected memory cells during access operations, leading to potential data loss.
Innovation Solution
A memory array with horizontal access lines and self-selecting memory cells, where each memory cell is isolated by a dielectric material and contacted by a single word line and bit line, preventing unwanted voltage transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are coupled with multiple word lines in conventional memory arrays, then access operations can be performed, but voltage transfer occurs between adjacent selected and unselected memory cells leading to reduced reliability and potential data loss
Solution Approach 1:
The memory array is segmented into distinct cell groups with isolated bit lines for each group. Each bit line is coupled to word lines and memory cells within a specific cell group only, preventing voltage transfer to adjacent cell groups. This segmentation approach maintains access functionality while eliminating the harmful voltage transfer effect.
Solution Approach 2:
Dielectric material is introduced as an intermediary between adjacent cell groups to electrically isolate their bit lines. This intermediary prevents direct voltage transfer between selected and unselected cells in adjacent groups, while still allowing each bit line to perform its intended access function within its own cell group.
2Reliability
If conventional memory array architecture is used, then manufacturing and operation are simpler, but voltage transfer causes data loss and reliability issues
Solution Approach 1:
The memory array is divided into multiple isolated cell groups, each with dedicated bit lines. This segmentation prevents voltage transfer between groups while maintaining a relatively simple access mechanism within each group, balancing reliability improvement with architectural complexity.
Solution Approach 2:
The memory array architecture transitions from a two-dimensional planar layout to a three-dimensional structure with vertically stacked cell groups separated by dielectric layers. This dimensional change enables electrical isolation between groups while maintaining efficient access paths within each group, improving data retention without excessive complexity.
Data Source
AI summary
Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.