Self-Selecting Memory Layer with Ferroelectric Traps
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high-performance, high-capacity memory storage with efficient manufacturing processes, particularly in miniaturization, low power consumption, and multi-functionality, as they require separate memory and selection elements which complicate integration and increase costs.
Innovation Solution
A semiconductor device with a self-selecting memory layer that operates as both a memory element and a selection element, utilizing a ferroelectric layer with deep traps and shallow traps formed by doping, allowing for different resistance states based on voltage applied, thereby simplifying the manufacturing process and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory and selection elements are used, then reliable data storage and selection functions are achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the memory element and selection element into a single integrated structure. The memory cell includes a first electrode, a second electrode, and a memory layer that simultaneously provides both memory storage and selection functionality, eliminating the need for separate selection transistors and reducing device complexity while maintaining reliable data storage
Solution Approach 2:
The memory layer is designed to perform multiple functions: it serves as both the storage element (retaining data through resistance states) and the selection element (enabling or disabling current flow based on applied voltage). This multi-functional design reduces the number of components needed while ensuring both storage reliability and selection capability
2Quantity of substance
If more memory cells are integrated, then storage capacity increases, but current leakage between adjacent cells increases
Solution Approach 1:
The patent applies different properties to different regions of the memory layer. Specifically, the memory layer has locally varied resistance characteristics that enable selective activation of individual memory cells. By controlling the local electrical properties and using voltage-dependent conductivity, the structure allows current to flow only through selected cells while blocking leakage current in non-selected adjacent cells, thus enabling high-density integration without significant current leakage
3Volume of moving object
If miniaturization is pursued, then device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes voltage as a control parameter to adjust the electrical properties of the memory layer dynamically. By applying different voltage levels, the memory layer transitions between different resistance states and conductivity levels, enabling precise control of memory cell behavior without requiring extremely tight physical dimensional control. This parameter-based control approach relaxes manufacturing precision requirements while enabling miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient data storage with reduced current leakage between memory cells, simplified manufacturing, and cost savings by integrating memory and selection functions into a single layer, while maintaining nonvolatile data storage through polarization states.
Implementation Method 1
a ferroelectric layer exhibiting deep traps for trapping conductive carriers
Implementation Method 2
a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer
Implementation Method 3
a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data
Implementation Method 4
having different resistance states according to a polarization state of the ferroelectric layer
Data Source
AI summary
A semiconductor device may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes a ferroelectric layer exhibiting deep traps for trapping conductive carriers and a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer.