Self-Selecting Memory Device Multi-Level Resistance Control
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Solution Overview
Problem
Existing memory devices struggle to implement multi-level memory efficiently due to limitations in their structural design and material properties, which affect their ability to vary resistance states in response to different voltage conditions.
Innovation Solution
A memory device comprising first and second electrodes, a self-selecting memory layer made of chalcogenide-based material with ovonic threshold switching characteristics, and a resistive memory layer, configured to implement multi-level resistance states by adjusting pulse polarity, number of pulses, pulse height, and pulse width of the applied voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a cross-point memory device structure is used with a 2-terminal selector and memory device connected in series, then the memory cell size is reduced in plan view, but the device complexity increases due to the need for additional components and series connection configuration
Solution Approach 1:
The patent combines the selector and memory device into a single self-selecting memory device (SSM) that performs both functions simultaneously. The chalcogenide-based material with ovonic threshold switching characteristic enables the device to function as both a selector (controlling current flow) and a memory element (storing resistance states), thereby eliminating the need for separate 2-terminal selector and memory device components while reducing the overall memory cell area.
Solution Approach 2:
The self-selecting memory device achieves multi-functionality by simultaneously providing selector functionality (threshold switching behavior) and memory storage functionality (multi-level resistance states). The single device responds to different voltage conditions to exhibit both selection characteristics and data storage capabilities, reducing structural complexity while maintaining the cross-point architecture benefits.
2Productivity
If existing memory devices are used to implement multi-level memory, then the structural design limitations prevent efficient multi-level implementation, but changing the structure increases device complexity
Solution Approach 1:
The patent implements multi-level memory by changing the resistance state of the self-selecting memory device through controlled voltage pulses. By varying parameters such as pulse polarity, number of pulses, pulse height, and pulse width, the device can be programmed to different resistance levels corresponding to multiple data states. This approach enables efficient multi-level memory implementation without requiring complex structural modifications, as the same SSM structure is utilized with different electrical programming conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory device effectively achieves multi-level resistance states, enhancing integration density and improving memory performance by leveraging the unique properties of the self-selecting memory layer and resistive memory layer.
Implementation Method 1
a self-selecting memory layer between the first and second electrodes, including a chalcogenide-based material, having an ovonic threshold switching characteristic, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto
Implementation Method 2
a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto
Data Source
AI summary
Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.