Self-Selecting Memory Cell Read Sequence for Error Reduction
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Solution Overview
Problem
Traditional memory devices face challenges in scaling down while maintaining low error rates, as error correction mechanisms increase costs and complexity, especially in systems with high error rates, and current technologies struggle to accurately read memory cells with overlapping threshold voltage distributions.
Innovation Solution
The use of self-selecting memory cells with phase change or chalcogenide materials that exhibit different threshold voltages based on programming and read polarity, allowing for a read sequence involving multiple voltage pulses to distinguish between logic states and reduce errors by enlarging the sensing window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction mechanisms are implemented in traditional memory devices, then error rates are reduced, but system cost increases
Solution Approach 1:
The patent extracts and removes the need for complex error correction mechanisms by using self-selecting memory cells that inherently provide error-free operation through their unique read sequence methodology, thereby reducing system cost while maintaining reliability
Solution Approach 2:
The memory cells perform self-verification through the read sequence process, where the first and second reads inherently validate data integrity without requiring external error correction circuits, making the system self-correcting and reducing overall complexity
2Reliability
If error correction mechanisms are implemented in traditional memory devices, then error rates are reduced, but space on memory die is occupied
Solution Approach 1:
The patent removes the need for dedicated error correction circuitry on the memory die by utilizing self-selecting memory cells with a specialized read sequence that provides inherent error detection and correction capabilities, freeing up valuable die space
Solution Approach 2:
The read sequence mechanism serves multiple functions simultaneously: it reads data from memory cells, verifies data integrity, and corrects errors all within a single operational sequence, eliminating the need for separate error correction hardware components
3Reliability
If error correction mechanisms are implemented in traditional memory devices, then error rates are reduced, but data retrieval time increases
Solution Approach 1:
The patent performs preliminary error detection and correction during the read sequence process itself, rather than requiring separate post-read verification steps, thereby reducing total data retrieval time while maintaining high reliability
Solution Approach 2:
The error detection and correction operations continue seamlessly alongside the data read operations in the read sequence, eliminating idle verification time and maintaining continuous productive action throughout the data retrieval process
4Length of moving object
If traditional memory devices are scaled smaller, then device size is reduced, but error rates increase
Solution Approach 1:
The patent changes the operational parameters of scaled memory devices by implementing a specific read sequence with controlled voltage pulses and timing, which compensates for scaling-induced errors and maintains high reliability in miniaturized devices
Solution Approach 2:
The patent employs dynamic voltage pulse adjustment in the read sequence, adapting pulse magnitudes and durations based on the scaled device characteristics to optimize reading accuracy and reduce errors in smaller memory devices
5Reliability
If read sequence with multiple voltage pulses is applied, then sensing window is enlarged and error rates are reduced, but reading process complexity increases
Solution Approach 1:
The patent segments the reading process into distinct sequential steps (first read, second read, comparison) that are simple and well-defined, making the overall complex process manageable and implementable without requiring overly sophisticated control circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate reading of memory cells with reduced error rates by differentiating between logic states even when threshold voltage distributions overlap, thereby minimizing the reliance on error correction mechanisms and enhancing the reliability of memory operations.
Implementation Method 1
the memory cell exhibits a first threshold voltage in response to the first read voltage having a first polarity and a second threshold voltage in response to the second read voltage having a second polarity opposite to the first polarity
Implementation Method 2
self-selecting memory cells with phase change or chalcogenide materials that exhibit different threshold voltages based on programming and read polarity
Data Source
AI summary
A method for reading memory cell, comprising the steps of applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, based on the first threshold voltages, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, wherein the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, based on the second threshold voltages, associating a second logic state to one or more cells of the plurality of memory cells, applying a third read voltage to the plurality of memory cells, wherein the third read voltage has the same polarity of the first and second read voltages and is applied at least to a group of memory cells that, during the application the second read voltage, have been reprogrammed to an opposite logic state, detecting third threshold voltages exhibited by the plurality of memory cells in response to application of the third read voltage, and based on the third threshold voltages, associating one of the first or second logic state to one or more of the cells of the of the plurality of memory cells. A related circuit, a related memory device and a related system are also disclosed.