Self-Synchronized Sense Amplifier for Low-Voltage Memory
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Solution Overview
Problem
Existing sense amplifiers for non-volatile memory cells, particularly in EEPROM and Flash memories, face challenges in reliability and performance at low supply voltages, and previous designs that do not use reference cells are not suitable for voltages less than 1.2 V, leading to reduced speed and reliability.
Innovation Solution
A sense amplifier circuit that precharges a bit line coupled to a memory cell, biases latch circuitry with a differential voltage, and activates the latch based on the memory cell current to produce an output signal indicating the direction of the switch, allowing for efficient reading of memory cells even at low supply voltages without the need for reference cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If reference cells are employed in differential amplifier sense amplifiers, then measurement precision is improved, but device complexity and testing time increase
Solution Approach 1:
The patent removes the reference cell array from the sense amplifier architecture, extracting the reference function and replacing it with a self-synchronized latch-based sensing mechanism that uses the bit line voltage swing itself as the reference, thereby eliminating the need for separate reference cells and reducing device complexity
Solution Approach 2:
The sense amplifier uses its own internal voltage swing on the bit line to provide the reference level for comparison, making the system self-sufficient without external reference cells. The latch circuit automatically synchronizes to the bit line voltage transitions, enabling self-synchronized operation that eliminates the need for external clocking and reference structures
2Measurement precision
If standard differential amplifier sense amplifiers are used, then measurement precision is improved, but speed and reliability deteriorate at supply voltages less than 2 V
Solution Approach 1:
The patent changes the operating parameters by using a latch circuit that triggers on voltage swings rather than continuous differential comparison. This allows the sense amplifier to operate reliably at lower supply voltages (below 2V) where conventional differential amplifiers fail, while maintaining speed through the fast-switching latch mechanism that responds to voltage transitions
3Device complexity
If fully asynchronous sense amplifiers without reference cells are used, then device complexity is reduced, but reliability deteriorates at low supply voltages
Solution Approach 1:
The latch circuit incorporates feedback through its cross-coupled transistor structure, where the output of each transistor feeds back to control the other. This feedback mechanism ensures stable operation and reliable switching at low supply voltages by maintaining proper biasing conditions and preventing unwanted oscillations, thereby improving reliability while keeping the structure simple
4Measurement precision
If reference cells are programmed during testing, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent eliminates the reference cell programming step entirely by removing the reference cell array from the architecture. The self-synchronized latch-based sense amplifier performs accurate current sensing without requiring pre-programmed reference cells, thereby eliminating the time-consuming programming phase while maintaining measurement precision
Data Source
AI summary
A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to memory cell current. There is also a means for producing an output signal indicating the direction of switch. A method of reading a memory cell comprises precharging a first bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the first bit line and a second node. The latch circuitry is then activated and the latch circuitry switches according to the memory cell current. An output signal indicating the direction of the latch circuitry's switch is then produced.