Self-Synchronizable Network for Large-Scale Chip Clocking
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Solution Overview
Problem
Existing clock distribution methods in large-scale networks, such as MPSoCs and MIMO systems, face challenges with communication latencies, power consumption, and synchronization issues due to limitations in globally asynchronous locally synchronous (GALS) and globally synchronous clocking techniques, especially with significant time delays and diverse phase detectors.
Innovation Solution
A network of interconnected nodes with controllable oscillators and controllers that adjust synchronization signals to achieve stable synchronized states through time-continuous self-organized synchronization, using phase-locked loops (PLLs) with tunable time delays and feedback mechanisms to synchronize phases across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a master clock based clock tree is used for globally synchronous design, then communication latencies between cores are reduced, but the clock signals have to be transmitted over millimeter ranges which causes bottlenecks for speed, power and reliability
Solution Approach 1:
The network is divided into multiple interconnected nodes, each with its own controllable oscillator, eliminating the need for a single master clock and long-distance signal transmission. Each node operates semi-autonomously while maintaining synchronization through local interactions.
Solution Approach 2:
Each node generates its own synchronization signal through a controllable oscillator and automatically adjusts its phase by comparing it with signals from other nodes, eliminating the need for centralized clock distribution and reducing transmission distances.
2Device complexity
If GALS clocking is used to separate clocking of processing blocks, then clock tree is simplified and clock generation on-chip is allowed, but additional communication latencies are introduced between disjoint clock domains
Solution Approach 1:
Multiple semi-autonomous clock domains are merged into a synchronized network through phase comparison and frequency adjustment, maintaining the benefits of distributed clock generation while eliminating the latency penalties of disjoint clock domains.
Solution Approach 2:
The system dynamically adjusts the frequency of each node's oscillator based on phase differences detected from neighboring nodes, allowing adaptive synchronization that responds to changing network conditions and maintains low latency.
3Reliability
If traditional globally synchronous clocking circuits are used, then all cores share one master clock, but the clock trees consume significant power and become too difficult for large MPSoCs with many cores
Solution Approach 1:
The single master clock is segmented into multiple distributed oscillators, each serving a local node. This eliminates the need for power-hungry long-distance clock distribution while maintaining synchronization through local phase comparison and frequency adjustment.
Solution Approach 2:
Each node self-generates its clock signal and autonomously adjusts its frequency to match the network synchronization frequency, eliminating the need for a power-consuming master clock distribution network across the entire chip.
4Reliability
If mutually connected PLL networks are used without time delay consideration, then synchronized states can be achieved, but the solution cannot be applied to networks with significant time delays between nodes
Solution Approach 1:
The system explicitly incorporates time delay as a adjustable parameter in the frequency adjustment equation, allowing the synchronization frequency to adapt to the actual transmission delays in the network. This makes the solution applicable to networks with significant and varying time delays between nodes.
Data Source
AI summary
A solution for synchronizing a network comprising a plurality of interconnected nodes provides a stable synchronized state, especially for large scale networks. Signal transmission speed and the length of each interconnection of the network is configured to cause a delay of the signals received by a node from the other node of the interconnection which is larger than one millionth of the free-running period of the controllable oscillator of the receiving node such that Network-wide synchronization of oscillators is achieved for all nodes of the network in a continuous self-organized process in interaction with the other node of the network.