Self-Synchronized Chip Link Across Independent Clock Domains
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Solution Overview
Problem
In 3D stacked chip-to-chip communication systems, the transmission of a common clock signal is challenging, especially at high frequencies, and existing solutions require dedicated clock channels or synchronizers, limiting the use of distinct and non-related clock domains.
Innovation Solution
A self-synchronized communication system using a capacitive or resistive channel with an asynchronous input stage and a synchronous output stage, eliminating the need for a common clock signal and dedicated clock channels, and incorporating a charge pump transmitter to compensate signal degradations, allowing data transmission to be synchronized with a clock signal without shared clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal or dedicated clock channel is used for synchronization, then reliable data transmission between stacked chips is achieved, but the system complexity increases and flexibility is reduced
Solution Approach 1:
The patent extracts the synchronization function from the traditional common clock signal approach and implements it through a self-synchronized receiver that autonomously adapts to the transmitter's clock domain. This eliminates the need for dedicated clock channels and external synchronizers, reducing system complexity while maintaining reliable data transmission between independently clocked stacked chips.
Solution Approach 2:
The receiver is designed with self-synchronization capability, automatically adapting to the transmitter's clock frequency and phase without requiring external clock signals or synchronizers. This self-service approach allows each chip to operate in its own clock domain while ensuring reliable communication, thereby reducing overall system complexity.
2Reliability
If a common clock signal is distributed across stacked chips, then synchronized communication is achieved, but the adaptability to different clock domains is reduced
Solution Approach 1:
The receiver incorporates dynamic clock domain adaptation mechanisms that allow it to automatically adjust to different transmitter clock frequencies and phases. This dynamic capability enables communication between independently clocked chips with different clock domains while maintaining synchronized data transmission, thereby enhancing both reliability and adaptability.
Solution Approach 2:
The system allows each chip to operate with its own clock parameters (frequency and phase) without requiring a common clock signal. The self-synchronized receiver adapts to the transmitter's clock parameters through automatic detection and adjustment, enabling flexible communication across different clock domains while ensuring reliable synchronized transmission.
3Adaptability or versatility
If internal synchronizers are added to handle clock differences, then data transmission between independently clocked chips is enabled, but the device complexity increases
Solution Approach 1:
The patent merges the synchronization function into the receiver's core architecture, eliminating the need for separate external synchronizers. The self-synchronized receiver integrates clock domain adaptation and data reception in a single unit, reducing the number of discrete components and simplifying the overall system design while supporting independent clock domains.
Solution Approach 2:
The self-synchronized receiver is designed as a universal interface that can handle multiple clock domains and transmission conditions without requiring different hardware components. This multi-functional design eliminates the need for dedicated synchronizers for each clock domain configuration, reducing design complexity while maintaining versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable and efficient chip-to-chip data transmission without requiring a common clock signal or dedicated clock channels, allowing for the use of independently clocked synchronous devices and improving communication performance by ensuring synchronized data transmission across different clock domains.
Implementation Method 1
connected to each other through a channel of the capacitive or resistive type
Data Source
AI summary
A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.