Self-Synchronous Security Gating for Side-Channel Resistant ICs
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Solution Overview
Problem
Existing integrated circuits (ICs) are vulnerable to side-channel attacks, particularly power supply and electromagnetic attacks, which can compromise security by revealing sensitive information through power consumption patterns and electromagnetic radiation.
Innovation Solution
The implementation of Attack Resilient Computation Circuits (ARCCs) that include security gating circuits and synchronization mechanisms to inhibit signal propagation until computation is complete, using security gating timing circuits (SGTC) and secure flip-flops (SFFs) to prevent power glitches and electromagnetic leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If security gating circuits are added to inhibit signal propagation until computation is complete, then side-channel attack resistance is improved, but device complexity increases
Solution Approach 1:
The computation circuit is divided into multiple computation stages with security gating circuits inserted between them. Each gating circuit independently controls signal propagation for its specific stage, allowing targeted security protection without requiring complete redesign of the entire circuit. This segmentation enables incremental security enhancement while managing complexity.
Solution Approach 2:
Security gating circuits act as intermediary components between computation stages, controlling signal flow based on synchronization signals. These gating circuits serve as mediators that enable secure computation by blocking premature signal propagation while maintaining normal circuit operation when security conditions are met.
2Reliability
If synchronization signals are used to gate computation stages, then power supply glitches are prevented, but computation speed decreases
Solution Approach 1:
Synchronization signals are generated in advance to predict when computation stages will complete. By proactively gating signals before potential glitches can occur, the system prevents power supply instability without waiting for actual errors to manifest. This preliminary action reduces the need for reactive corrections that would further slow computation.
Solution Approach 2:
The synchronization mechanism uses feedback from computation stage completion signals to control gating circuits. When a computation stage finishes, it generates a synchronization signal that triggers the next gating circuit to open, allowing continuous flow of data. This feedback-based control ensures that gating only occurs when necessary, minimizing speed penalties while maintaining power stability.
Data Source
AI summary
An Attack Resilient Computation Circuit (ARCC) in an integrated circuit (IC) includes a first computation stage, a second computation stage, and security circuitry. The first computation stage is configured to process one or more signals so as to produce one or more outputs, the first computation stage having multiple signal propagation paths. The second computation stage is configured to receive and process the outputs of the first computation stage. The security circuitry is configured to generate a synchronization signal indicating that propagation of the signals in the first computation stage has completed, and to inhibit the second processing stage from processing the outputs of the first processing stage for a time interval derived from the synchronization signal.