Self-Terminating DRAM Buffer Asynchronous Termination Control
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Solution Overview
Problem
Conventional memory systems face inefficiencies in signal transmission and power consumption due to synchronous termination methods, which are hindered by differences in latency characteristics among various DRAM devices, leading to undesirable signal traversal and increased power usage.
Innovation Solution
Implementing an asynchronous termination scheme within a memory buffer device that controls termination timing based on DRAM command signals rather than host controller ODT signals, allowing each DRAM device to self-terminate and manage its own clock cycles, thereby reducing redundant cycles and improving signal quality and compatibility among heterogeneous devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous termination method is used, then signal transmission quality is improved, but power consumption increases and latency differences cause signal traversal issues
Solution Approach 1:
The patent implements dynamic termination control where the memory buffer device asynchronously adjusts termination resistance based on detected DRAM device latency characteristics. The system transitions from static synchronous termination to dynamic asynchronous termination, allowing each DRAM device to be terminated at its optimal timing moment, thereby reducing unnecessary power consumption while maintaining signal quality.
Solution Approach 2:
The patent changes the termination resistance parameter dynamically based on the operational state and latency characteristics of individual DRAM devices. By monitoring command signals and adjusting termination resistance in real-time rather than using fixed synchronous termination, the system optimizes both signal quality and power consumption for each specific device configuration.
2Reliability
If synchronous termination is used, then signal quality is improved, but termination turnaround time increases
Solution Approach 1:
The memory buffer device performs preliminary detection of DRAM device latency characteristics and pre-configures appropriate termination settings before actual data transmission occurs. This preliminary action allows the system to skip unnecessary termination cycles and achieve faster termination turnaround time while maintaining signal quality through proper initial configuration.
Solution Approach 2:
The system dynamically adjusts termination timing based on real-time detection of DRAM command signals and device-specific latency characteristics. Rather than using fixed synchronous termination intervals, the system adapts termination timing to match actual device operation, significantly reducing termination turnaround time without compromising signal integrity.
3Adaptability or versatility
If heterogeneous DRAM devices are connected to common data bus, then system versatility is improved, but signal interference increases
Solution Approach 1:
The patent applies local quality control by implementing individualized termination strategies for each DRAM device on the common data bus. Each device receives customized termination settings based on its specific latency characteristics and operational state, allowing heterogeneous devices to coexist without mutual interference. The memory buffer device monitors and adjusts termination parameters locally for each device independently.
Solution Approach 2:
The system enables each DRAM device to essentially self-configure its termination parameters by detecting its own command signals and latency characteristics. The memory buffer device facilitates this self-service approach by monitoring command signals and automatically applying appropriate termination settings for each device, eliminating the need for manual configuration and preventing signal interference among heterogeneous devices.
Data Source
AI summary
A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface.