Self-Test Cells for Integrated Circuit Defect Localization

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Solution Overview

Problem

Conventional built-in self-test (BIST) mechanisms in integrated circuit devices provide insufficient granularity to identify defective functional components within partitions, limiting the ability to react effectively to faults and requiring increased design effort and die area for higher granularity.

Innovation Solution

The integration of self-test cells configured into scan-chains within integrated circuit devices allows for finer granularity in detecting defective components by configuring the device into multiple self-test configurations, enabling targeted fault detection and response without significant design or area increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If self-test partition granularity is increased to identify defective functional components more precisely, then measurement precision is improved, but device complexity and design effort increase significantly

Engineering Contradiction:

Improvedefect identification precisionVSAvoiddesign effort

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the integrated circuit device into multiple self-test cells, each containing functional components grouped in a tree structure. This segmentation allows defects to be localized to specific cells and tree paths without requiring fine-grained partitioning of the entire device, thereby improving measurement precision while controlling device complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension by organizing functional components into tree structures within self-test cells. Instead of using a single level of fine-grained partitions, the invention uses multiple levels of hierarchy (cell level, tree level, path level) to achieve precise defect localization without proportionally increasing complexity at each level.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Measurement precision

If self-test partition granularity is increased to identify defective functional components more precisely, then measurement precision is improved, but die area increases

Engineering Contradiction:

Improvedefect identification precisionVSAvoiddie area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent merges multiple functional components into shared self-test cells that contain common test resources such as scan chains and signature analyzers. By combining test functionality at the cell level rather than providing dedicated test resources for each individual component, the invention achieves fine-grained defect identification without proportionally increasing die area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Self-test cells are designed to be multi-functional, containing test resources that can be shared across multiple functional components within the cell. This universality allows a single cell to test multiple components through different tree paths, reducing the overall die area required compared to having dedicated test structures for each component.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If conventional BIST mechanisms are used, then device complexity is kept low, but measurement precision for defect identification is insufficient

Engineering Contradiction:

Improvetest mechanism complexityVSAvoiddefect location precision

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic reconfigurability within self-test cells, allowing the selection of different scan chains and tree paths based on the specific testing requirements. This dynamic capability enables precise defect localization without requiring a static, overly complex test structure for every possible defect scenario, thereby improving measurement precision while managing device complexity.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9529047B2Integrated circuit device and method of performing self-testing within an integrated circuit device

Publication Date: 2016.12.27 NXP USA INC

AI summary

IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration.