Self-test Controller for ICs with Dynamic Clock Frequency Scheduling
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Solution Overview
Problem
Complex integrated circuits (ICs) face challenges in achieving efficient self-test management, particularly in safety-critical applications where real-time monitoring and minimal power consumption are essential.
Innovation Solution
A self-test controller circuit is implemented, comprising a master finite state machine and a set of BIST finite state machines, which schedules and configures multiple BIST controllers to perform tests at varying clock frequencies, optimizing test time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple BIST controllers are used to test different components of the IC, then test coverage is improved, but device complexity increases
Solution Approach 1:
A single self-test controller is designed to perform multiple functions by configuring and controlling different types of BIST controllers (logic BIST, memory BIST, analog BIST) through a unified architecture. The controller can adaptively configure test parameters, clock frequencies, and test sequences for various IC components, eliminating the need for separate dedicated controllers for each test type while maintaining comprehensive test coverage.
Solution Approach 2:
The self-test controller dynamically changes operating parameters such as clock frequency, test pattern selection, and test sequence configuration to accommodate different test requirements. By adjusting these parameters, the single controller can effectively manage diverse BIST operations across logic circuits, memories, and analog components, resolving the contradiction between test coverage and device complexity.
2Reliability
If BIST tests are performed at multiple clock frequencies to ensure comprehensive testing, then test reliability is improved, but test time increases
Solution Approach 1:
The self-test controller implements dynamic test execution by adaptively selecting clock frequencies based on the specific test requirements and detected circuit conditions. Rather than executing fixed sequential tests at multiple frequencies, the controller dynamically adjusts test parameters in real-time, optimizing the balance between test reliability and test time by performing comprehensive testing at the most appropriate frequencies for each specific test scenario.
Solution Approach 2:
The controller changes clock frequency parameters dynamically during test execution based on the test phase and detected circuit responses. This parameter adaptation allows the system to achieve comprehensive test coverage at optimized frequencies rather than performing exhaustive multi-frequency testing, thereby reducing overall test time while maintaining test reliability.
3Reliability
If BIST tests are executed frequently in safety-critical applications for real-time monitoring, then system safety is improved, but power consumption increases
Solution Approach 1:
The self-test controller implements periodic self-test execution with configurable intervals, allowing the system to balance safety monitoring requirements against power consumption constraints. Instead of continuous testing, the controller performs BIST operations at optimized periodic intervals, ensuring system safety through regular monitoring while minimizing power consumption by keeping the system in low-power states between test cycles.
Solution Approach 2:
The controller dynamically adjusts test frequency and duration parameters based on system operational state and safety criticality levels. By changing these parameters adaptively, the system can intensify testing when safety concerns are higher and reduce testing intensity during normal operation, thereby maintaining system safety while optimizing power consumption across different operational scenarios.
Data Source
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AI summary
A method for managing self-tests in an integrated circuit, IC comprises: receiving (1004) built-in-self-test, BIST configuration data; configuring (1002) a first clock to a first frequency based on the BIST configuration data; performing (1012) a first BIST test at the first frequency; configuring (1006) a second clock to a second frequency that is different from the first frequency; and performing (1012) a second BIST test at the second frequency.