Self-Testing GFCI with Dynamic IC Mode Switching
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Solution Overview
Problem
Ground fault circuit interrupters (GFCIs) face challenges in meeting the UL943 standard's fault current levels and response timing requirements, particularly with existing ground fault detection ICs that exhibit variable response times for different fault magnitudes, and the need for automatic self-testing capabilities.
Innovation Solution
A self-testing GFCI device incorporating a fault circuit with a line monitoring circuit, line interrupting circuit, fault detector circuit, and a microcontroller that initiates self-tests across different half cycles of opposite polarity, using timing circuitry to control the discharge of a capacitor and ensure timely tripping within the UL943 specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an integrating type ground fault detection IC is used, then the GFCI trips in accordance with UL943 timing requirements for prescribed fault magnitudes, but the response time varies for different fault magnitudes resulting in longer response times for smaller faults
Solution Approach 1:
The patent changes the operating parameters of the ground fault detection IC by switching between integrating type and comparator type operation modes. The microcontroller configures the IC to use comparator mode during self-test operations, achieving fixed rapid response time regardless of fault magnitude, while allowing integrating mode for normal operation to meet UL943 timing requirements for various fault levels.
2Speed
If a comparator type ground fault detection IC is used, then the trip response time is consistently fast at approximately 2 ms, but the GFCI may not satisfy UL943 timing requirements for smaller magnitude faults
Solution Approach 1:
The patent implements dynamic operation mode switching where the ground fault detection IC can operate in either integrating type mode or comparator type mode based on the operational state. During normal operation, the integrating mode is used to meet UL943 timing requirements for various fault magnitudes. During self-test operations, the microcontroller switches to comparator mode to achieve fast fixed response time for test signal detection.
3Reliability
If automatic self-testing is implemented, then the device can verify proper operation and prevent false failures, but the testing procedure duration increases and may conflict with fault detection timing
Solution Approach 1:
The patent implements periodic self-testing where the microcontroller initiates self-test sequences at predetermined intervals during normal GFCI operation. The self-test uses the ground fault detection IC in comparator mode to rapidly detect test signals, minimizing test duration. The periodic nature allows the system to verify operational integrity without continuously blocking fault detection capabilities.
Solution Approach 2:
The patent performs preliminary configuration of the ground fault detection IC by the microcontroller before initiating self-test operations. The microcontroller pre-configures the IC for comparator mode operation and prepares the test circuitry, ensuring that the self-test can execute rapidly without delaying fault detection response when faults occur during or between test cycles.
4Productivity
If self-test is performed during normal operation, then continuous monitoring is maintained, but the GFCI may trip during self-test due to simulated faults being mistaken for actual faults
Solution Approach 1:
The patent implements feedback control where the microcontroller monitors the operational state and self-test status to dynamically control the ground fault detection IC mode. During self-test operations, the microcontroller provides feedback to switch the IC to comparator mode and disables normal fault tripping logic. This prevents false tripping during self-test while maintaining continuous monitoring capabilities through the self-test process itself.
Data Source
AI summary
A process for self testing a fault circuit includes disabling an actuator, performing a self-test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity, and determining whether the self-test was successful.