Self-time Circuitry for Dual-Rail Memory Power Optimization
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Solution Overview
Problem
Conventional self-time circuitry for memory devices fails to effectively track process corners variations in gate versus parasitic RC delays, leading to functional failures at faster corners and performance degradation at slower corners, and is ineffective for dual-rail memory devices, resulting in insufficient or surplus read and write margins.
Innovation Solution
A self-time circuitry that includes a tracking control circuit and dummy discharge cells (DDCs) coupled to both core and periphery power rails, generating tracking signals to adjust the self-time delay based on both core and periphery voltages, allowing for fine-grained control of memory timing and power optimization in dual-rail memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional self-time circuitry is used to control memory timing, then power consumption is reduced through automatic shutdown, but timing accuracy deteriorates due to inability to track process corner variations
Solution Approach 1:
The self-time circuitry is segmented into multiple process corner-specific circuits (fast corner circuit, slow corner circuit, etc.), each optimized for specific process conditions. This allows the system to select the appropriate circuit segment based on detected process corners, maintaining timing accuracy across variations while preserving power-saving functionality.
Solution Approach 2:
The system dynamically selects and switches between different self-time circuits based on detected process corners and operating conditions. This dynamic adaptation ensures timing accuracy is maintained across process variations while the automatic shutdown function continues to save power when memory operations are complete.
2Reliability
If self-time delay is increased to ensure read and write margins at fast process corners, then reliability improves, but performance deteriorates at slower process corners
Solution Approach 1:
Different self-time delay values are assigned to different process corner circuits. Fast corner circuits use smaller delays optimized for speed, while slow corner circuits use larger delays to ensure adequate margins. The system applies the appropriate local delay characteristic based on the detected process corner, ensuring both reliability and performance are optimized for each condition.
Solution Approach 2:
The self-time delay parameter is changed based on process corner detection. The system monitors process variations and adjusts the delay parameter by switching to the appropriate pre-configured circuit, ensuring read and write margins are sufficient at fast corners without degrading performance at slower corners.
3Loss of energy
If dual-rail memory architecture is used to separate core and periphery voltages, then power optimization is improved, but timing control becomes ineffective with conventional self-time circuitry
Solution Approach 1:
The self-time circuitry is designed with multiple voltage domain compatibility. The circuit can operate with different voltage levels on core and periphery rails, detecting process corners and generating appropriate timing signals regardless of the voltage separation. This universal design maintains timing control effectiveness while preserving the power optimization benefits of dual-rail architecture.
Solution Approach 2:
The self-time circuitry acts as an intermediary between the separated core and periphery voltage domains. It detects process corners and generates timing signals that coordinate operations across both voltage domains, ensuring proper timing control despite the voltage separation that enables power optimization.
Data Source
AI summary
A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.