Self-Timed Single-Track Buffer Circuit for FPGA Signal Loads
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Solution Overview
Problem
Conventional single track circuits are not suitable for FPGA routing environments due to significant signal loads and capacitive loads, leading to issues with clock skew and communication in high-speed synchronous designs.
Innovation Solution
The implementation of self-timed single track circuits with separate pulse generator portions that sense the output stage's state to shut off the input stage pulse generator, allowing for independent sizing of forward and acknowledgment circuitry, and using bidirectional rails for communication between stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional single track circuits are used in high-speed synchronous designs, then clock distribution is required, but clock skew and communication problems occur due to signal loads and capacitive loads
Solution Approach 1:
The patent employs periodic pulse generation where the input stage generates a pulse in response to an input signal, and the output stage generates an acknowledgment pulse periodically. This periodic action replaces the continuous clock distribution approach, allowing asynchronous operation that avoids clock skew issues while maintaining reliable signal transmission at high speeds
Solution Approach 2:
The circuit is segmented into distinct input stage and output stage components with separate pulse generation capabilities. This segmentation allows each stage to operate independently with its own timing characteristics, eliminating the need for centralized clock distribution and reducing the impact of capacitive loads on overall system reliability
2Productivity
If the input stage pulse generator is kept on continuously, then signal transmission is maintained, but overlapping pulses cause short circuit current
Solution Approach 1:
The output stage provides feedback to the input stage through the acknowledgment pulse. When the output stage generates an acknowledgment pulse in response to receiving a signal, this feedback mechanism causes the input stage pulse generator to shut off. This feedback loop ensures continuous signal transmission while preventing overlapping pulses that would cause short circuit current
Solution Approach 2:
The circuit uses self-service timing where the output stage's acknowledgment pulse automatically controls the input stage pulse generator's operation. The system regulates itself by having the output stage's state directly influence the input stage, eliminating the need for external control signals and preventing harmful overlapping pulses through autonomous operation
Data Source
AI summary
An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.