Self-Timed Clocked Processor Architecture Using Critical Path Oscillator
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Solution Overview
Problem
Synchronous digital processors face challenges in minimizing power consumption while avoiding timing errors due to variations in temperature and voltage, which can cause propagation delays to exceed clock periods, leading to incorrect data output and malfunctions.
Innovation Solution
Implementing a self-timed clocked processor architecture with dynamic voltage/frequency scaling, using a critical path oscillator to model the processor's critical path and adjust operating voltage to ensure propagation delays are within the clock period, and utilizing a power manager to dynamically adjust voltage and frequency to maintain accurate data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor operates at near-threshold voltage to minimize power consumption, then power consumption is reduced, but propagation delay varies by a factor of up to 100 over temperature range and by a factor of five or more between gates at a single temperature, making it difficult to estimate minimum required clock frequency
Solution Approach 1:
The processor uses its own critical path delay characteristics to generate the clock signal through a ring oscillator, eliminating the need for external clock sources. The ring oscillator's delay is deliberately made longer than the critical path delay to ensure proper timing, allowing the processor to self-adjust to temperature and voltage variations without external intervention.
Solution Approach 2:
The system implements feedback by using the critical path delay itself to determine the clock frequency. The ring oscillator continuously adapts its output frequency based on the actual propagation delay through the critical path, creating a closed-loop system that automatically compensates for environmental variations.
2Speed
If a fixed external clock signal is used to clock the processor, then synchronous operation is maintained, but propagation delay may exceed the clock period under varying temperature and voltage conditions, leading to timing errors and incorrect data output
Solution Approach 1:
The system transitions from a fixed external clock to a dynamic self-timed clock that automatically adjusts its frequency based on real-time critical path delay measurements. This dynamic adaptation allows the clock period to always exceed the propagation delay, preventing timing errors across varying operating conditions.
3Reliability
If the clock frequency is reduced to accommodate maximum propagation delay, then timing errors are avoided, but power consumption increases due to lower operating efficiency
Solution Approach 1:
The system dynamically changes the clock frequency parameter based on actual critical path delay conditions rather than using a fixed conservative value. By adjusting the clock frequency to match the actual propagation delay, the system achieves timing accuracy while maximizing operating efficiency and minimizing power consumption.
Data Source
AI summary
There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.