Self-Timed Circuit Delay Selection for Dynamic Voltage Scaling
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Solution Overview
Problem
Timing-constrained circuits, such as self-timed and racing paths in integrated circuits, face challenges in maintaining optimal performance across varying operating conditions due to increased propagation delays at lower voltages, leading to glitches and functional failures, as existing designs rely on excessive timing margins that are not dynamically adaptable.
Innovation Solution
The solution involves dynamically adjusting the delay of self-timed circuits and racing paths based on current operating conditions by using multiple timing chains with different delay characteristics, allowing for the selection of optimal delay margins through a multiplexer, enabling dynamic voltage and frequency scaling to maintain performance across PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sufficient timing margins are included in self-timed and racing paths to ensure reliable operation over the entirety of expected operating voltage range, then reliability is improved, but performance deteriorates due to unnecessarily large timing margins under some operating conditions
Solution Approach 1:
The patent implements dynamic delay adjustment by providing multiple timing chains with different delay characteristics and selecting the appropriate chain based on current operating conditions. This allows the circuit to adapt timing margins dynamically rather than using fixed excessive margins, thereby maintaining reliability across voltage ranges while optimizing performance under each specific condition.
Solution Approach 2:
The patent changes the delay parameter of timing chains based on operating voltage conditions. By providing timing chains with different delay characteristics and selecting among them, the system adjusts timing parameters to match actual operating conditions, avoiding the performance penalty of fixed excessive timing margins while ensuring reliability across the full voltage range.
2Reliability
If delay elements are designed to provide sufficient delay even in worst operating condition through static fuse programming, then reliability is improved, but adaptability deteriorates due to lack of dynamic flexibility to respond to actual operating conditions
Solution Approach 1:
The patent replaces static fuse programming with dynamic selection among multiple timing chains. Each timing chain is designed to provide sufficient delay under specific operating conditions, and a multiplexer dynamically selects the appropriate chain based on current voltage and temperature conditions. This provides both the reliability of sufficient delay and the adaptability to respond to actual operating conditions.
Solution Approach 2:
The patent segments the timing function into multiple independent timing chains, each optimized for specific operating conditions. Instead of a single static timing path, the system divides timing functionality across multiple chains with different delay characteristics, allowing dynamic selection to match actual conditions while ensuring each segment provides adequate delay when selected.
3Reliability
If timing margins are increased to account for propagation delay variations with PVT conditions, then reliability is improved, but speed deteriorates due to excessive delays under non-worst-case conditions
Solution Approach 1:
The patent changes timing parameters dynamically by selecting among multiple timing chains with different delay characteristics. Each chain is optimized for specific PVT conditions, allowing the system to use minimal necessary timing margins for each condition rather than worst-case margins for all conditions, thereby maintaining timing constraint satisfaction while maximizing signal propagation speed under each specific condition.
Solution Approach 2:
The patent applies different timing margin characteristics to different operating conditions through local selection of appropriate timing chains. Each timing chain has locally optimized delay characteristics matched to specific PVT conditions, allowing the system to use appropriate timing margins only where needed rather than applying excessive margins universally, thus improving speed while maintaining reliability.
Data Source
AI summary
A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions.