Self-Timed Processor Extension for Variable Latency Instructions
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Solution Overview
Problem
Processors with pipeline architectures face inefficiencies due to latency issues with instructions that do not have a predetermined execution time, limiting their ability to implement user-defined instructions effectively.
Innovation Solution
A configurable processor with a processor core extension that allows for the execution of user-defined, self-timed instructions through an interface logic and handshake protocol, enabling the inclusion of instructions without prior knowledge of their execution latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor uses a pipeline architecture with predetermined latency instructions, then processing efficiency is improved for deterministic operations, but the processor cannot effectively execute instructions with variable execution times
Solution Approach 1:
The patent introduces a dynamic timing mechanism where the processor pipeline can adapt to variable instruction execution times. The extension logic executes user-defined instructions with indeterminate latency, and the ready status signal dynamically indicates when execution completes, allowing the pipeline to continue processing other instructions during the variable execution time without stalling.
Solution Approach 2:
The patent introduces extension interface logic as an intermediary between the processor core and extension logic. This intermediary coordinates operations using a handshake protocol with a ready status signal, which mediates the interaction between the fixed-pipeline processor and the variable-time extension instructions, enabling both deterministic and indeterminate latency operations to coexist.
2Adaptability or versatility
If user-defined extension instructions are added to a processor, then adaptability and customization are improved, but device complexity increases due to additional interface logic and coordination mechanisms
Solution Approach 1:
The extension interface logic implements a universal handshake protocol that can handle multiple types of user-defined extension instructions with different execution characteristics. The ready status signal serves as a universal indicator for various extension instructions, allowing the same interface mechanism to coordinate diverse custom instructions without requiring separate coordination logic for each instruction type.
3Reliability
If the processor waits for variable-time instructions to complete before proceeding, then execution accuracy is maintained, but processing speed and efficiency deteriorate due to pipeline stalls
Solution Approach 1:
The patent extracts variable-time instruction execution from the main processor pipeline by implementing it in extension logic separate from the core pipeline. This allows the pipeline to continue processing deterministic instructions at full speed while the extension logic handles variable-time instructions independently, with results communicated back through the ready status signal without causing pipeline stalls.
Data Source
AI summary
A processor for executing configurable instructions and a method of configuring the processor are disclosed. In one embodiment, the processor includes (i) a processor core to execute preconfigured instructions and (ii) a processor core extension to execute user-defined extension instructions that are configurable instructions. The user-defined extension instructions may include an autonomous instruction with varying execution cycles based on source data and an operation performed. The processor core extension employs extension interface signals as a handshake protocol to operate together with the processor core without knowing any priori knowledge of how many processor clock cycles that the autonomous instruction will take to complete.