Self-Timed Memory RC Delay Extension for Write Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Self-timed memories face challenges in achieving optimal performance and efficiency in write operations, particularly in high-density bit-cells, due to varying RC delays across different voltage domains, which affect Power, Performance, and Area (PPA) metrics, and traditional tuning methods fail to address these challenges uniformly.
Innovation Solution
Implementing a self-timed path (STP) circuit with resistor-capacitor (RC) delay tracking mechanisms, including extended dummy wordlines and bitlines, to optimize write operations by fine-tuning RC delays specifically for write cycles, while maintaining read access time and overall system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional tuning methods are used for write operations, then read access time is maintained, but write operation performance is suboptimal due to varying RC delays across voltage domains
Solution Approach 1:
The patent segments the write operation tuning process into multiple independent RC delay tracking paths (first RC delay path and second RC delay path) that can be optimized separately for different voltage domains. This allows each path to be tuned independently, resolving the contradiction between maintaining read access time and optimizing write performance across varying voltage conditions.
Solution Approach 2:
The patent applies local quality by creating voltage-domain-specific RC delay tracking mechanisms. The first RC delay path is optimized for first voltage domains while the second RC delay path is optimized for second voltage domains, allowing each region to have tailored tuning parameters that match its specific electrical characteristics, thereby improving write performance without compromising read access time.
2Productivity
If RC delays are extended to improve write operations, then write performance increases, but PPA metrics are impacted
Solution Approach 1:
The patent implements dynamic RC delay tracking where the delay elements can be adjusted based on actual operating conditions and voltage domains. This dynamic tuning allows the system to extend RC delays only when and where necessary for write operations, rather than using fixed extended delays that would continuously impact PPA metrics, thus improving write performance while minimizing energy consumption.
3Manufacturing precision
If extended dummy wordlines and bitlines are added for RC delay tracking, then write operation precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the RC delay tracking circuitry universal by designing the first and second RC delay paths to serve multiple functions: they track RC delays for write operations, provide timing information for precise data writing, and can be configured for different voltage domains. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving write precision while limiting the increase in device complexity.
Data Source
AI summary
According to one implementation, a method includes determining a self-timed path (STP) circuit based on a first resistor-capacitor (RC) delay and a logic delay, wherein the first RC delay includes a delay associated with a first dummy wordline (DWL) and a dummy bitline (DBL); and extending the STP circuit based on a second RC delay, wherein the second RC delay includes a delay associated with an extended DWL.