Self-Timed Data Sampler for Metastability Recovery
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Solution Overview
Problem
Existing solutions for passing signals between different timing domains, which rely on synchronous circuits with 'brute force' synchronizers, suffer from metastable states that lead to unstable outputs, high current consumption, and performance impact due to unnecessary delays.
Innovation Solution
A data sampler circuit with a metastable detect circuit that allows the data storage circuit to recover from metastable states without a chain of flip-flops, using a gated clock or enable signal to prevent metastable states from propagating, and adaptive recirculation of data samples until stability is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a chain of flip-flops is used as a synchronizer, then metastability is handled, but system performance is degraded due to constant delay
Solution Approach 1:
The synchronizer dynamically adjusts its operation mode based on whether metastability is detected. When metastability is detected, it enters a recovery mode with extended delay; when not detected, it operates in normal mode with minimal delay. This dynamic adaptation resolves the contradiction by making the delay conditional rather than constant.
Solution Approach 2:
The circuit changes the timing parameters of the synchronizer based on the metastable recovery signal. The delay through the flip-flop chain is extended only when metastability occurs, rather than maintaining a fixed conservative delay always. This parameter change allows optimal performance in normal conditions while ensuring reliability when needed.
2Reliability
If a chain of flip-flops is used as a synchronizer, then metastability is handled, but power consumption increases due to high current draw
Solution Approach 1:
The power consumption of the synchronizer is dynamically controlled based on metastability detection. The flip-flops are enabled only when metastability is detected and disabled during normal operation. This dynamic control resolves the contradiction by consuming high power only when necessary for metastability recovery, rather than continuously.
Solution Approach 2:
The circuit changes the operational state of the flip-flops based on the metastable recovery signal. When metastability is detected, the flip-flops are enabled to handle the recovery; when not detected, they are disabled to minimize power consumption. This parameter change in enable/disable state resolves the power consumption contradiction.
3Adaptability or versatility
If synchronous circuits are used with brute force synchronizers, then signal passing between timing domains is achieved, but system performance is impacted
Solution Approach 1:
The synchronizer dynamically adapts its delay characteristic based on metastability detection. Instead of always imposing a fixed delay that impacts performance, the delay is extended only when metastability occurs. This dynamic behavior maintains signal passing capability while minimizing performance impact during normal operation.
4Reliability
If the data sample signal is recirculated, then metastable states are resolved, but additional delay is introduced
Solution Approach 1:
The circuit changes the timing parameters of the data sample signal based on metastability detection. When metastability is detected, the signal is recirculated with extended delay to allow recovery; when not detected, the signal passes through with minimal delay. This conditional parameter change resolves the contradiction between reliable recovery and time efficiency.
Data Source
AI summary
A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. A comparison of input data to sampled data is used to determine the existence of a metastable state.