Self-Timed Multi-Core Processor Dynamic Core Activation
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Solution Overview
Problem
Multi-core processors face inefficiencies due to high power consumption and heat generation, making them unsuitable for low-power applications like mobile devices, as all cores are clocked even when not processing instructions, leading to wasted energy and thermal issues.
Innovation Solution
A self-timed parallelized multi-core processor design where each core can be dynamically activated or deactivated for each instruction, using a shared instruction fetch unit and token-based asynchronous logic units to reduce power consumption and heat, allowing only necessary cores to operate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all cores are clocked continuously to ensure processing capability, then processing speed and responsiveness are improved, but power consumption and heat generation increase significantly
Solution Approach 1:
The patent implements dynamic core activation where cores are clocked only when needed for processing. The system transitions from static continuous clocking to dynamic on-demand clocking, allowing cores to be activated or deactivated based on workload requirements. This resolves the contradiction by maintaining processing speed when needed while reducing power consumption during idle periods.
Solution Approach 2:
The system employs periodic core activation where cores are clocked in periodic intervals or bursts rather than continuously. Instructions are fetched and executed in periodic batches, allowing cores to remain idle between periods. This approach maintains necessary processing capability while significantly reducing overall power consumption and heat generation.
2Productivity
If the number of cores is increased to enhance processing power, then computational capacity is improved, but power consumption and heat generation worsen
Solution Approach 1:
The patent implements a shared instruction fetch unit that serves multiple cores universally. Instead of each core having its own fetch unit, a single shared unit broadcasts instructions to multiple cores. This reduces the total component count and power consumption while maintaining high computational capacity through parallel execution across multiple cores.
Solution Approach 2:
The system uses broadcast copying where a single instruction fetch result is copied and distributed to multiple cores simultaneously. Rather than duplicating the fetch operation across all cores, the instruction is fetched once and then copied to relevant cores, reducing redundant operations and power consumption while maintaining parallel processing capability.
3Device complexity
If a shared instruction fetch unit is used to reduce complexity and power consumption, then device complexity and energy use are reduced, but instruction delivery to specific cores requires additional coordination mechanisms
Solution Approach 1:
The patent implements feedback mechanisms where cores provide status information back to the shared instruction fetch unit. This feedback allows the fetch unit to intelligently determine which cores need instructions and when to broadcast them, optimizing instruction delivery efficiency without requiring complex per-core fetch units. The feedback loop enables coordinated operation between the shared fetch unit and multiple cores.
Data Source
AI summary
A self-timed parallelized multi-core processor has an instruction decoder unit for receiving a program code instruction, determining an operating code and latency for the instruction, and assigning a loop index to the instruction. An instruction decomposer creates a primitive by decomposing the instruction, replacing the loop index with a core index, and broadcasting the primitive. Self-timed processing cores each having a unique core index compare the core index to their unique processing core index. The processing cores act on the primitive when their processing core index is within a threshold of the core index.