Self-Timed Superscalar Processor with Distributed Clocking
Solution Overview
Problem
Superscalar processors face challenges in reducing power consumption, particularly due to the global clock tree, which consumes a significant portion of the processor's power and wastes energy when function units are idle.
Innovation Solution
The implementation of self-timed function units that operate independently, eliminating the need for a global clock tree by using distributed clock-on-demand circuits, allowing instructions to be executed out-of-order and generating results unconstrained by program counter order, and utilizing a central resource manager for allocation and commitment of execution results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global clock tree is used to synchronize function units, then the processor can maintain stable operation and instruction order, but power consumption increases significantly (20%-30% of total power)
Solution Approach 1:
The patent divides the processor into multiple independent pipelines, each with its own local clock generator. This segmentation eliminates the need for a single global clock tree, reducing power consumption while maintaining operational stability through distributed clock synchronization.
Solution Approach 2:
Each pipeline is equipped with local clock-on-demand circuits that generate clock signals only when needed for specific instructions. This local approach replaces the uniform global clocking scheme, reducing unnecessary power consumption in idle function units while maintaining reliability where needed.
2Measurement precision
If the global clock tree operates continuously to synchronize function units, then timing accuracy is maintained, but power is wasted when function units are idle
Solution Approach 1:
The patent implements clock-on-demand circuits that generate clock signals periodically only when instructions are ready for execution. This replaces continuous global clocking, maintaining timing accuracy for active operations while eliminating wasted energy during idle periods through event-triggered clock generation.
Solution Approach 2:
Each pipeline's local clock generator autonomously determines when clock signals are needed based on instruction readiness and execution status. This self-service mechanism eliminates dependence on the global clock tree, maintaining timing precision while reducing power consumption by activating clocks only when function units require them.
3Productivity
If multiple function units operate in parallel without program counter order constraints, then instruction-level parallelism increases and throughput improves, but maintaining instruction order becomes more complex
Solution Approach 1:
The patent introduces a result commitment unit as an intermediary between the parallel pipelines and the final output. This mediator receives results from multiple pipelines operating in parallel, reorders them according to program counter sequence, and commits them in the correct order. This enables high throughput from parallel execution while managing the complexity of maintaining instruction order through a dedicated coordination mechanism.
Data Source
AI summary
A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.