Self-Timed Processor Logic Using Unate Gates and Global Acknowledge
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Solution Overview
Problem
Synchronous digital processors face challenges in power consumption and speed due to their reliance on a common clock signal, while asynchronous self-timed processors with multi-rail null convention logic and threshold gates face inefficiencies in gate delay and complexity.
Innovation Solution
Implementing self-timed processors with multi-rail null convention logic and unate gates, which reduce gate delay and power consumption by eliminating the need for a common clock signal and using fewer gates, while ensuring input and null completeness through acknowledge signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous digital processors use a common clock signal to coordinate operations, then operational synchronization is achieved, but power consumption increases and maximum operating speed is limited
Solution Approach 1:
The patent extracts and removes the common clock signal from the processor architecture, transitioning to an asynchronous design where each operational block operates independently without a centralized clock, thereby eliminating clock distribution overhead and enabling higher speeds with lower power consumption
Solution Approach 2:
The processor implements dynamic operation where each block operates at its own optimal speed based on local data availability and computation requirements, rather than being constrained by a fixed global clock frequency, allowing flexible speed adaptation and improved energy efficiency
2Reliability
If asynchronous processors use multi-rail null convention logic with threshold gates, then delay insensitivity is achieved, but gate delay increases and circuit complexity increases
Solution Approach 1:
The processor is divided into independent operational blocks that can be implemented with simpler logic gates, where each block handles specific functions separately rather than requiring complex threshold gates throughout the entire circuit, reducing overall complexity while maintaining delay insensitivity
Solution Approach 2:
The patent changes the logic paradigm from traditional threshold-based NCL to unate gate-based logic with modified signal conventions, altering the operational parameters to achieve delay insensitivity through different mechanisms that require fewer gates and less complexity
3Productivity
If asynchronous processors use unate gates instead of threshold gates, then gate delay decreases and power consumption decreases, but ensuring input completeness and null completeness becomes more challenging
Solution Approach 1:
The patent implements feedback mechanisms through acknowledge signals that track the validity state of data throughout the processor, ensuring that unate gates receive complete and valid inputs before producing outputs, thereby maintaining input completeness without requiring complex threshold gate logic
Solution Approach 2:
The system performs preliminary validation of input data using acknowledge signals before data enters the unate gate logic, ensuring that all necessary inputs are ready and valid in advance, which prevents incomplete computation and maintains reliability with simpler gates
Data Source
AI summary
There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.