Self-Trimming Memory Device Using Trimmable Delay Elements
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Solution Overview
Problem
Integrated circuits face challenges in maintaining setup and hold timing parameters across varying temperature and supply conditions, leading to potential malfunction and metastability issues, especially in applications with wide temperature and voltage ranges, where traditional trimming methods are time-consuming and not universally effective.
Innovation Solution
A non-volatile memory device with self-trimming capabilities, employing programmable or trimmable delay elements inserted upstream of clock and data inputs to adjust timing and impedance matching, utilizing a dummy row for optimization and storing optimal settings for different conditions, allowing for re-centering of signals affected by drift and ensuring proper functionality across temperature and voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional factory trimming is performed on each single IC to overcome process spread, then manufacturing precision is improved, but productivity deteriorates due to time-consuming die-per-die testing
Solution Approach 1:
The patent uses a dummy row that copies the structure and timing characteristics of actual memory rows to perform trimming operations. By testing on this replicated dummy row instead of actual production chips, the system can determine optimal timing parameters without compromising productivity of the main manufacturing line.
Solution Approach 2:
The trimming operation is performed in advance on a dummy row during manufacturing, and the resulting timing parameters are stored for use during actual operation. This preliminary trimming eliminates the need for time-consuming testing on each subsequent IC, thereby improving both precision and productivity.
2Reliability
If setup time is increased to ensure proper data sampling, then reliability is improved, but hold time requirements worsen due to opposite parameter movement with temperature variations
Solution Approach 1:
The patent employs trimmable delay elements that can dynamically adjust their delay characteristics based on operating conditions. By changing the delay parameter of these elements, the system can compensate for temperature-induced shifts in setup and hold times, maintaining both reliability and timing precision across varying conditions.
Solution Approach 2:
The system transitions from fixed timing parameters to dynamic, adjustable timing parameters through the use of trimmable delay elements. These elements can be reconfigured based on temperature and process variations, allowing the setup and hold times to adapt rather than remain static, thus resolving the contradiction between opposing parameter movements.
3Device complexity
If fixed timing parameters are used in integrated circuit design, then device complexity is reduced, but adaptability deteriorates under wide temperature and voltage range variations
Solution Approach 1:
The patent introduces trimmable delay elements that can dynamically adjust their characteristics based on operating conditions. This dynamic capability allows the circuit to adapt to wide temperature and voltage ranges without requiring completely different designs for each condition, thus improving adaptability while maintaining reasonable complexity through standardized adjustable components.
Solution Approach 2:
The system performs self-trimming by automatically adjusting the delay elements based on detected operating conditions such as temperature and process variations. This self-service capability eliminates the need for external intervention or complex control systems, maintaining device complexity at acceptable levels while achieving wide adaptability.
Data Source
AI summary
An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.