Self-tuning Delay Circuit for Multi-Voltage Domain Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiple voltage domain circuits, voltage level variations between different domains can cause discrepancies in signal path delays, potentially rendering the circuit non-functional, especially in memory systems where precise timing is critical for data integrity and power conservation.
Innovation Solution
A self-tuning delay circuit is implemented, comprising delay elements supplied by both the higher and lower voltage domains, which adjusts the delay output to match the greater delay between the two domains, ensuring that sense amplifiers do not activate before valid data is asserted on bit lines, thereby maintaining operational integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multiple voltage domains are used to conserve power, then power consumption is reduced, but signal path delay discrepancies occur between domains
Solution Approach 1:
A delay circuit is introduced as an intermediary component in the sense path to compensate for delay discrepancies between voltage domains. The delay circuit receives a sense signal and outputs a delayed sense signal, effectively mediating the timing mismatch caused by operating different circuit portions at different voltage levels.
Solution Approach 2:
The delay circuit dynamically adjusts its delay characteristic based on the operating conditions of the memory system. By changing the delay parameter of the sense path, the system compensates for voltage-domain-induced timing variations, ensuring reliable operation across different power consumption modes.
2Use of energy by moving object
If voltage levels are reduced to conserve power, then power consumption decreases, but circuit operation reliability deteriorates
Solution Approach 1:
The memory system is segmented into multiple voltage domains: a first voltage domain for the cell core unit and a second voltage domain for peripheral circuits. This segmentation allows independent voltage control, enabling power conservation in peripheral circuits while maintaining higher voltage for critical memory operations to ensure reliability.
Solution Approach 2:
The delay circuit acts as an intermediary that bridges the timing gap created by different voltage domains. It ensures that control signals from the lower-voltage peripheral circuits are properly synchronized with the higher-voltage cell core unit operations, maintaining overall system reliability.
3Speed
If sense amplifiers activate before valid data is asserted, then access speed increases, but data integrity is compromised
Solution Approach 1:
The delay circuit is configured to provide a predetermined delay to the sense signal, ensuring that the sense amplifiers are activated at the appropriate time after data assertion. This preliminary timing adjustment prevents premature activation while maintaining optimal access speed.
Solution Approach 2:
The delay circuit's delay characteristic is determined based on feedback regarding the timing relationship between data assertion and sense amplifier activation. This feedback mechanism ensures that the delay is precisely tuned to maintain data integrity without unnecessarily slowing down access operations.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.