Self-Tuning PLL Circuit for Jitter and Lock Time Control
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Solution Overview
Problem
Phase-locked loop (PLL) circuits in electronic devices exhibit varying jitter profiles due to voltage dependencies, leading to inconsistent clock signals across different silicon wafers and ICs, even with identical designs.
Innovation Solution
A self-tuning PLL circuit with adaptive-bandwidth optimization, featuring dual operational modes (frequency-locked and phase-locked) that iteratively optimize parameters like DCO gain and filter coefficients, and stores these for future use, reducing jitter and lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PLL circuits are used with fixed parameters, then the circuit design is simple and manufacturing is easy, but the jitter varies across different silicon wafers and ICs due to voltage dependencies
Solution Approach 1:
The PLL circuit performs self-calibration by automatically measuring its own jitter characteristics and adjusting its parameters without external intervention. The calibration sequence measures jitter at multiple voltage levels and iteratively optimizes DCO gain and filter coefficients to minimize jitter, enabling the circuit to self-optimize its performance for each specific IC.
Solution Approach 2:
The invention dynamically changes key parameters including DCO gain, loop filter coefficients, and calibration voltage levels based on measured jitter characteristics. By iteratively adjusting these parameters during calibration, the system optimizes jitter performance for each specific IC while maintaining manufacturability through software-based parameter optimization rather than hardware redesign.
2Reliability
If PLL parameters are optimized for each IC to reduce jitter, then jitter consistency improves, but the calibration process increases manufacturing time and complexity
Solution Approach 1:
The PLL circuit performs calibration during the manufacturing test phase before the IC leaves the factory. The calibration sequence executes measurements and parameter optimizations in advance, storing the optimized parameters in non-volatile memory. This preliminary action ensures jitter consistency is established during manufacturing rather than requiring complex real-time adjustments later.
Solution Approach 2:
The invention replaces traditional mechanical or hardware-based parameter adjustment mechanisms with software-controlled digital calibration. Instead of requiring physical adjustments or complex analog circuits, the system uses digital measurement and control to optimize parameters, simplifying the manufacturing process while achieving precise jitter control.
3Loss of time
If the PLL circuit includes adaptive bandwidth optimization and dual operational modes, then lock time and jitter are reduced, but the circuit complexity increases
Solution Approach 1:
The PLL circuit dynamically switches between frequency-locked and phase-locked operational modes during calibration based on the current state and requirements. The system adapts its bandwidth and control strategy in real-time, using frequency locking for coarse tuning and phase locking for fine optimization, thereby reducing lock time while managing complexity through intelligent mode transition.
Solution Approach 2:
The calibration process is segmented into distinct phases: initial frequency acquisition, iterative jitter measurement at multiple voltage levels, and final parameter optimization. By dividing the calibration into manageable segments with specific objectives, the system achieves rapid lock time without overwhelming control logic complexity, as each segment handles a specific task.
4Measurement precision
If multiple calibration voltage levels are used to optimize jitter, then measurement precision improves, but the calibration time increases
Solution Approach 1:
The calibration sequence periodically measures jitter at multiple voltage levels in a systematic pattern rather than continuously monitoring all parameters simultaneously. By using periodic sampling at strategically selected voltage points, the system achieves precise jitter characterization without requiring constant measurement, thereby balancing measurement precision with acceptable calibration time.
Data Source
AI summary
Embodiments may relate to techniques or circuitry for the control of a clock signal by a phase-locked loop (PLL) circuit. The technique may include the identification of a first parameter related to a gain of a digitally controlled oscillator (DCO) and a second parameter related to a resolution of a time-to-digital converter (TDC). The technique may then include the identification of a third parameter related to filter coefficients of a loop filter of the PLL circuit based on the first and second parameter. The circuit may then output a clock signal based on the first, second, and third parameters. Other embodiments may be described or claimed.